EP0168770A2 - Bus pour données optiques utilisant une méthode d'accès statistique - Google Patents

Bus pour données optiques utilisant une méthode d'accès statistique Download PDF

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Publication number
EP0168770A2
EP0168770A2 EP85108599A EP85108599A EP0168770A2 EP 0168770 A2 EP0168770 A2 EP 0168770A2 EP 85108599 A EP85108599 A EP 85108599A EP 85108599 A EP85108599 A EP 85108599A EP 0168770 A2 EP0168770 A2 EP 0168770A2
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EP
European Patent Office
Prior art keywords
data
output
clock
input
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85108599A
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German (de)
English (en)
Other versions
EP0168770A3 (fr
Inventor
Viktor Dipl.-Ing. Dr. Bodlaj
Steven Dr. Moustakas
Hans-Hermann Dipl.-Phys. Dr. Rer. Nat. Witte
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Siemens AG
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Siemens AG
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Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0168770A2 publication Critical patent/EP0168770A2/fr
Publication of EP0168770A3 publication Critical patent/EP0168770A3/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/27—Arrangements for networking
    • H04B10/278—Bus-type networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/44—Star or tree networks

Definitions

  • the present invention relates to an optical data bus with a statistical access method according to the preamble of patent claim 1.
  • a data bus of the type mentioned has already been proposed in the earlier patent application VPA 82 P 1509.
  • a specific example of a statistical or asynchronous access method is the CSMA / CD access method (Carrier Sense Multiple Access Collision Detection, see Comm. Of the ACM, July 1 976, Vol. 19, No. 7, pages 395 to 404).
  • the bit rate on the transmission link is the same as the data bit rate to be transmitted.
  • the encoder assigned to a transmitter consists of a scrambler, which is required a) for recovering the clock in the receiver and b) for logically differentiating the "do not send data" state from the "send data” state.
  • the decoder consists of a descrambler. So-called header bits must be placed in front of the start of the user data and the end of the user data is marked by end-of-data marking bits in the form of a specific bit sequence.
  • the clock is recovered, for example, by a PLL circuit from the bit sequence entering a receiver.
  • the receiver control is constructed in such a way that the correct clock is recovered after the header bit sequence, and the header bits and the end of data marking bits are separated from the actual user data.
  • the object of the present invention is to obtain control circuits for the communication part which are as simple as possible in the case of an optical data bus of the type mentioned, in particular with CSMA / CD access methods.
  • This type of coding makes it possible to simplify the control circuits in the transmitter part, in the receiver part and also in a collision detection part and to construct them with fewer components. Also, no markings are required for the start and end of the user data, which must be separated from the user data in the recipient group.
  • the data bus according to the invention requires twice as much bandwidth as the data bus proposed. However, its structure is simpler and therefore less susceptible to interference: It can be advantageously implemented wherever the optical transmission system with transmitters, fibers and receivers still has so much reserve that the system can be operated with 100% redundancy.
  • a particularly simple and advantageous embodiment of the data bus according to the invention can be seen in claim 2, in which the Manchester decoder only requires two D flip-flops, two EXOR gates, three delay lines and an inverter.
  • a preferred embodiment of the data bus according to claim 2 is specified in claim 3.
  • the NRZ data recovered by the Manchester decoder of a data bus according to the invention as claimed in claim 2 or 3 are somewhat out of phase with the clock contained in the supplied data. To eliminate this phase shift, it is expedient to design such a data bus according to claim 4.
  • This embodiment according to claim 4 also has the advantage that the clock recovery device can be realized by only one additional EXOR gate, which is connected as specified in claim 5.
  • the valid signal can also be recovered very easily with a monostable multivibrator according to claim 6.
  • a bus state detection device can also be implemented very easily.
  • Such a data bus is specified in claim 7.
  • the circuit structure according to FIG. 1 consists of several transmitters S, of which only one is shown, of the star coupler SK and several receivers E, of which only one is also shown.
  • the transmitter S contains a Manchester encoder MK and a downstream LED driver LT, which is an LED (light-emitting Diode, for example laser diode) drives.
  • the clock and the NRZ data are fed to the Manchester encoder MK, from which it generates the Manchester-coded data which are fed to the LED driver LT.
  • the Manchester coding can be obtained from the clock and the NRZ data using an EXOR gate, for example.
  • the manchester-coded data supplied to the LED driver LT are supplied to the star coupler SK via an optical fiber. They are fed to the receivers E from the star coupler SK via other fibers.
  • the manchester-coded message is received in each receiver E by a photo receiver FE.
  • a PIN or APD diode can be used as the photo receiver FE.
  • the Manchester-coded signal generated by the photodiode receiver FE is fed to a photodiode amplifier which is provided and not shown in the photodiode receiver and which can be an AC amplifier (AC-coupled amplifier) with a relatively low bandwidth when the data are encoded in Manchester.
  • the small bandwidth of the photodiode amplifier results in a good signal / noise ratio, which is of great advantage for weak photodiode signals.
  • the signals preamplified in the photodiode receiver FE are fed to a post-amplifier NV in order to amplify them to a level which is required for conversion into TTL signals with the aid of a voltage comparator which is provided in a voltage comparator / Manchester decoder SD provided in the receiver E for the recovery of the NRZ -Data, the clock and the valid signal is included.
  • the signals converted to the TTL level are decoded in the Manchester decoder MD of the voltage comparator / Manchester decoder SMD.
  • the voltage comparator / Manchester decoder SMD is constructed in such a way that not only the NRZ data are recovered, but also the clock which is required for processing the data.
  • the Manchester-coded data from the post-amplifier NV of the receiver E are fed to the voltage comparator SKo of the voltage comparator / Manchester decoder SMD, the structure of which need not be described in more detail, and at its output 8 the Manchester-coded data in the form of TTL signals are sent to the Manchester decoder MD via its input A. are fed.
  • the delay lines VL which delay the signals of the manchester-coded data by T / 2, 4T / 5 and T, where T denotes the cycle length of the cycle, and the EXOR gates E1 to E3 are used to recover the NRZ data from the fed-in manchester-coded data and the two D flip-flops FF1 and FF2.
  • the 4K / 5 and T delayed coded data from the outputs v2 and.v3 of the delay lines VL are fed in parallel to the two inputs e31, e32 of the EXOR gate E3, whose output signal at the output Ta is sent to the flip-flop FF1 via its clock input CK as a clock is fed.
  • the undelayed and the T / 2 delayed Manchester-coded data from input A and output v1 of delay lines VL are fed in parallel to the two inputs e11, e12 of EXOR gate E 1 , the output signals of which Output B is fed to an input e21 of the EXOR gate E2 as data.
  • the other input e22 of the EXOR gate E2 is constantly at a high level, which is derived from the TTL level of +5 volts.
  • the EXOR gate E2 acts as an inverter.
  • the output signals from the output C of the EXOR gate E2 are fed to the D flip-flop via its D input and CLR input.
  • the output signal from the Q output of the flip-flop FF1 is fed to the clock input CK of the downstream D-flip-flop FF2 as a clock.
  • This phase shift can be eliminated by a delay of T / 5 in a delay element V, which is required for the recovery of the clock and the valid signal limiting the respective data packet.
  • the two D flip-flops FF1 and FF2 essentially have the task of regenerating the data in the rhythm of the clock. They are switched accordingly and clock and data signals are fed to them accordingly.
  • the SN 74 S 86 module can be used for the EXOR gates E1 to E3 and for the D flip-flops with the SN 74 S 74 module from Texas Instruments Inc. (see, for example, The TTL-Data Book, p. 209 or p. 76; the inputs and outputs of the D flip-flop are as described on p. 76 of the book mentioned).
  • pulse trains are shown with each other over time t, as they occur in sequence at input A, at output v 1 of delay lines VL, at output B of EXOR gate E1, at output C of EXOR gate E2, at output v 2 of the delay lines VL, at the output v 3 of the delay lines VL, at the output Ta of the EXOR gate E3, at the Q output of the first D flip-flop FF1, in repetition at input A, at the Q output of the downstream D flip-flop FF2 and are present at the Q output of this flip-flop.
  • the following four pulse trains relate to other circuit parts, which will be referred to later.
  • pulse sequence III represents the bit sequence specified there in man-coded form.
  • the pulse train delayed by T / 2 at v1 and the pulse train at A are linked by EXOR gate E 1 , which results in the pulse train at B, which is inverted by EXOR gate E3, from which the pulse train at C results.
  • This pulse sequence at C which carries the data information, is fed to the D input of the D flip-flop FF1 and at the same time also to the clearing input CLR of this flip-flop.
  • the pulse sequence delayed by 4T / 5 compared to the pulse sequence A at v2 and the pulse sequence delayed by the full clock length T at v3 is linked by the EXOR gate E3, which results in the pulse sequence at Ta which, as the clock pulse sequence, corresponds to the clock input CK of the first D -Flipflops FF1 is fed. Due to its property as a D flip-flop, this first flip-flop FF1 switches so that the pulse train is produced at its output Q, which is shown in FIG. 4 at Q of FF1. Successive pulses of this pulse sequence at Q of FF1 are at a distance from each other that is equal to the pulse or clock duration T or an integer multiple thereof, and they mark in time the rising and falling edges of the associated pulses of the original NRZ data.
  • This pulse sequence at Q from FF1 is applied to the clock input CK of the downstream D flip-flop FF2, at the D input of which the Manchester-coded data is present at A without delay.
  • the downstream flip-flop FF2 switches due to its D property in such a way that the original NRZ data (see diagram II in FIG. 2) is produced at its Q output.
  • the pulse sequence at Q of FF2 in FIG. 4 is out of phase with the pulse sequence of the original NRZ data by 1 / 5T, in the sense of a lead. This can be compensated for by the delay element V, from the output v4 of which the original NRZ data in the phase of the clock are taken, which are shown in FIG. 4 at v4 and which correspond exactly to the pulse sequence II in FIG.
  • the recovered NRZ data from the output v4 is also used to recover the original clock in a clock recovery switching device which consists of a delay line for delaying a signal by half the clock length T / 2 and an EXOR gate E 4 , which is again with the module SN 74 S 86 can be realized.
  • the input coded at A and delayed by T / 2 at an input e41 of the EXOR gate E 4 is fed to the input 4 , while the other input e42 of the EXOR gate E 4 receives the NRZ data from the Output v4 of the delay element V are supplied without delay.
  • the clock pulse sequence of the original clock which is shown in FIG. 4 at a, is then output directly at the output a of the EXOR gate E 4 .
  • the validation signal shown at b in FIG. 4 is obtained from the clock pulses at a by the monostable multivibrator MF. This is triggered by the clock pulses from a and its time constant is determined by the duration of the clock pulse sequence, the output signal of the monostable multivibrator MF corresponding to the valid signal.
  • the specific structure of the monostable multivibrator will be described later in connection with similar multivibrators.
  • each participant who is involved in the optical star bus with the star coupler SK has a receiver E and a transmitter S with the associated Manchester encoder, Manchester decoder and amplifier.
  • the recovered clock the duration of which corresponds exactly to the duration of the data packets, which is determined by the valid signal, enables a relatively simple bus status detection.
  • the schematic structure of the corresponding bus state detection circuit is shown in FIG. 5. The circuit is built into a star bus according to Figure 1.
  • the main feature for the bus state detection is a phase / frequency discriminator PFD, on the one hand the transmission clock supplied to a transmitter S, with which the transmitted data is clocked and which is generated, for example, by a computer, and on the other hand a receiver clock supplied by the voltage comparator / Manchester decoder SMD is generated or recovered in the associated receiver E.
  • the transmission clock generated by the computer is fed to the phase / frequency discriminator PFD via an input T S and the reception clock from the receiver E via an input T E.
  • An output A 'of the phase / frequency discriminator PFD is zero if the transmit and receive clock at both inputs T S and T E match exactly in both the frequency and the phase.
  • the clocks at the inputs T S and T E of the phase / frequency discriminator PFD can only match exactly if the transmission clock applied to the input T S and the receiver clock applied to the input T E belong to the same subscriber, ie if the the receiver clock applied to the input T E comes from the data given by the own transmitter S which has been clocked with the transmission clock applied to the input T S (the clock frequencies of the individual subscribers differ slightly because the clock generators of the different subscribers are not coupled to one another) .
  • This logic zero is also passed on as logic 0 via an AND gate UG when a monostable multivibrator MF1 switches to logic 1 at its output Q 1 because of the receiver clock generated at its input e1. Since the output B 'of the AND gate UG has logic 0, the output Q 2 of a monostable multivibrator MF2 connected to its input e2 to the output B' of the AND gate UG and the output Q 3 of one having its input e3 the third monostable multivibrator MF3 connected to the output Q 2 of the second monostable multivibrator MF2 on logic.
  • the logical 0 at output Q 3 of the third monostable multivibrator MF3 signals that the bus is occupied with its own data.
  • the logical 0 at the output Q 3 of the third monostable multivibrator MF3 also appears when the bus is not occupied at all, because in this case, although the transmission clock appears at the output A 'of the phase / frequency discriminator PFD, the output B' of the AND gate UG remains at logic 0 and because output Q 1 of the first monostable multivibrator MF1 remains at logic 0 due to the missing receiver clock from receiver E.
  • both the clock frequency of the receiver clock from the Emp catcher E and its phase differ from the clock frequency and the phase of the transmission clock of the own transmitter S present at the input T S of the phase / frequency discriminator PFD.
  • a pulse sequence appears at the output A 1 of the phase / frequency discriminator PFD, the pulse length of which is a function of the frequency and phase difference of the clocks present at the inputs T S and T E of the phase / frequency discriminator PFD.
  • the output Q 1 of the first monostable multivibrator MF1 switches to logic 1 when there is a receiver clock at the input T E and thus also at its input e 1 , the pulse signal at the output A 'of the phase / frequency discriminator PFD up to the output B' of the AND gate UG transmitted.
  • the logical 1 at the output B 'of the UG is passed on via the second monostable multivibrator MF2 and the third monostable multivibrator MF3.
  • the logical 1 at output Q 3 of the third monostable multivibrator MF3 means that the bus is occupied by another participant.
  • circuitry measures can be used to prevent a transmitter from turning on for the time the bus is occupied.
  • the output Q 3 of the third monostable multivibrator MF3 via an inverter IG becomes an input e71 NAND gate NG supplied, at whose second input e72 the valid signal to be supplied to the Manchester encoder MK of the own transmitter S is given.
  • Sending the data from the Manchester encoder MK to the LED driver LT is only possible if Q 3 is logic 0 and a valid signal is sent.
  • the mode of operation of the bus state detection circuit according to FIG. 5 can be characterized by the following truth table for the bus state:
  • the output of the EXOR gate E 5 of each monostable multivibrator MF, MF1 and MF2 forms the output b, Q and Q 2 of the multivibrator in question.
  • the monoflop MP of each of these monostable multivibrators MF, MF1 and MF2 causes a phase shift of the clock applied to the input e, e1 and e2 of the respective multivibrator in such a way that the two inputs e51, e52 of the EXOR gate E5 are always at different logic levels , as long as the supplied clock signals last.
  • the time constant of the third monostable multivibrator MF3 is set in the third monostable multivibrator MF3 such that only errors that last over several bits are recognized as a collision.
  • the errors, which only last for a period of time that is less than the time constant of the third monostable multivibrator MF3, are registered as transmission errors via an error line.
  • the time constant of the third monostable multivibrator is expediently chosen to be an integer multiple of the pulse and clock duration T.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Electromagnetism (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Optical Communication System (AREA)
  • Dc Digital Transmission (AREA)
  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
EP85108599A 1984-07-19 1985-07-10 Bus pour données optiques utilisant une méthode d'accès statistique Withdrawn EP0168770A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3426683 1984-07-19
DE3426683 1984-07-19

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EP0168770A2 true EP0168770A2 (fr) 1986-01-22
EP0168770A3 EP0168770A3 (fr) 1988-05-04

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JP (1) JPS6139744A (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991001597A1 (fr) * 1989-07-25 1991-02-07 Sf2 Corporation Procede et circuit destines a decoder un signal en code manchester
EP0459289A1 (fr) * 1990-06-01 1991-12-04 Japan Aviation Electronics Industry, Limited Emetteur-récepteur optique
EP0495007A1 (fr) * 1989-10-02 1992-07-22 Codenoll Technology Corp Detection de collisions a l'aide d'infractions aux regles du code de manchester.
EP0557561A1 (fr) * 1992-02-28 1993-09-01 International Business Machines Corporation Liaison de données en série utilisant le codage NRZI et Manchester
EP0773653A3 (fr) * 1995-11-13 2001-04-18 Texas Instruments Incorporated Procédé et appareil de décodage de données codées en code Manchester
AU2008216966B2 (en) * 2003-04-25 2009-01-08 Apple Inc. An electronic apparatus including a transmitter
EP3232573B1 (fr) * 2012-05-29 2019-07-24 Sew-Eurodrive GmbH & Co. KG Procédé de décodage et décodeur

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US4864588A (en) * 1987-02-11 1989-09-05 Hillier Technologies Limited Partnership Remote control system, components and methods
JPH0621257Y2 (ja) * 1987-07-16 1994-06-01 三洋電機株式会社 固体撮像装置
JPH064596Y2 (ja) * 1987-08-03 1994-02-02 三洋電機株式会社 電荷結合型固体撮像装置
US5148333A (en) * 1988-12-21 1992-09-15 Sony Corp. Method for recording and/or reproducing a signal
JPH0636509B2 (ja) * 1990-06-22 1994-05-11 日本航空電子工業株式会社 光バス伝送方式
US5309475A (en) * 1991-10-01 1994-05-03 Abb Power T&D Company Inc. Data interchange network
KR100299540B1 (ko) * 1998-08-14 2001-10-27 서평원 맨체스터코드를이용한데이터전송방법및그장치
US7340183B2 (en) * 1998-11-17 2008-03-04 Broadwing Corporation Optical communications systems, devices, and methods
ATE378742T1 (de) * 2001-08-24 2007-11-15 Broadwing Corp Erzeugung eines subträgermodulierten optischen signals durch elektrooptische umwandlung eines manchester-kodierten signals
US7161992B2 (en) * 2001-10-18 2007-01-09 Intel Corporation Transition encoded dynamic bus circuit
US7224739B2 (en) * 2002-08-21 2007-05-29 Intel Corporation Controlled frequency signals
US7158594B2 (en) * 2002-08-21 2007-01-02 Intel Corporation Receivers for controlled frequency signals
US7305023B2 (en) * 2003-07-23 2007-12-04 Intel Corporation Receivers for cycle encoded signals
US7308025B2 (en) 2003-07-23 2007-12-11 Intel Corporation Transmitters providing cycle encoded signals
US7154300B2 (en) * 2003-12-24 2006-12-26 Intel Corporation Encoder and decoder circuits for dynamic bus
US7272029B2 (en) * 2004-12-29 2007-09-18 Intel Corporation Transition-encoder sense amplifier

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EP0098452A2 (fr) * 1982-07-01 1984-01-18 Siemens Aktiengesellschaft Circuit pour la détection de collisions de données dans un bus de données optique et circuit pour la détection de l'état libre du bus
US4450554A (en) * 1981-08-10 1984-05-22 International Telephone And Telegraph Corporation Asynchronous integrated voice and data communication system

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EP0098452A2 (fr) * 1982-07-01 1984-01-18 Siemens Aktiengesellschaft Circuit pour la détection de collisions de données dans un bus de données optique et circuit pour la détection de l'état libre du bus

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991001597A1 (fr) * 1989-07-25 1991-02-07 Sf2 Corporation Procede et circuit destines a decoder un signal en code manchester
EP0495007A1 (fr) * 1989-10-02 1992-07-22 Codenoll Technology Corp Detection de collisions a l'aide d'infractions aux regles du code de manchester.
EP0495007A4 (en) * 1989-10-02 1992-12-16 Codenoll Technology Corporation Collision detection using code rule violations of the manchester code
EP0459289A1 (fr) * 1990-06-01 1991-12-04 Japan Aviation Electronics Industry, Limited Emetteur-récepteur optique
EP0557561A1 (fr) * 1992-02-28 1993-09-01 International Business Machines Corporation Liaison de données en série utilisant le codage NRZI et Manchester
EP0773653A3 (fr) * 1995-11-13 2001-04-18 Texas Instruments Incorporated Procédé et appareil de décodage de données codées en code Manchester
AU2008216966B2 (en) * 2003-04-25 2009-01-08 Apple Inc. An electronic apparatus including a transmitter
AU2008216994B2 (en) * 2003-04-25 2009-01-08 Apple Inc. An adapter for media player
EP3232573B1 (fr) * 2012-05-29 2019-07-24 Sew-Eurodrive GmbH & Co. KG Procédé de décodage et décodeur

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EP0168770A3 (fr) 1988-05-04
US4663767A (en) 1987-05-05
JPS6139744A (ja) 1986-02-25

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