EP0141122A1 - Montage pour la mesure d'intervalles de temps courts - Google Patents

Montage pour la mesure d'intervalles de temps courts Download PDF

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Publication number
EP0141122A1
EP0141122A1 EP84110185A EP84110185A EP0141122A1 EP 0141122 A1 EP0141122 A1 EP 0141122A1 EP 84110185 A EP84110185 A EP 84110185A EP 84110185 A EP84110185 A EP 84110185A EP 0141122 A1 EP0141122 A1 EP 0141122A1
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EP
European Patent Office
Prior art keywords
output
flop
time
circuit
circuit arrangement
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Granted
Application number
EP84110185A
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German (de)
English (en)
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EP0141122B1 (fr
Inventor
Klaus Welzhofer
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Siemens AG
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Siemens AG
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Priority to AT84110185T priority Critical patent/ATE34852T1/de
Publication of EP0141122A1 publication Critical patent/EP0141122A1/fr
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Publication of EP0141122B1 publication Critical patent/EP0141122B1/fr
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time

Definitions

  • the invention relates to a circuit arrangement for measuring short times and for outputting the measured time in digital form, to which a start pulse indicating the start of the time to be measured and a stop pulse indicating the end of the time to be measured is supplied.
  • Computer-controlled test systems require fully automatic testing of individual electronic components, e.g. SSI, MSI, LSI, VLSI components etc., and assembled printed circuit boards, e.g. printed circuit boards, in addition to measuring devices for static measurement value acquisition, e.g. for level evaluation, measurement of currents and voltages etc. , increasingly also measuring devices for dynamic measured value acquisition, for example for measuring the period of pulses, the pulse width, the rise and fall times of pulses.
  • An example of this is the testing of ECL-LSI circuits, even in which / static module errors can only be detected by high-resolution measurement value acquisition (in the ps range) of the pulse edge time or the delay time at the device under test output.
  • the method required at least 2000 cycles with a cycle time of "10 / us. Measurements in single-shot operation could be carried out with fast counters. However, this method only led to measurement errors of less than 1% from times greater than 1 / us. Pulse edge measurements could not be carried out with them Until now, dynamic measurements have largely been dispensed with for reasons.
  • the object on which the invention is based is to provide a circuit arrangement for measuring short times, with which dynamic measurement problems can also be solved, in particular single-shot operation is possible and which works with a high measurement value resolution in the picosecond range.
  • This object is achieved in a circuit arrangement of the type mentioned in the introduction in that a first delay element is provided, which is supplied with the start pulse, and a second delay element is provided with a longer delay time than the first delay element, in which the stop pulse is supplied, in that the first Delay element with the set input of a bistable flip-flop, the second delay element is connected to the reset input of the bistable flip-flop, that the outputs of the bistable flip-flop are connected to a time / voltage converter containing a discharge circuit, which generates a voltage proportional to time, and that at the output the time / voltage converter, an analog / digital / converter with an adjustable voltage threshold is connected, which is set so that when the inputs of the circuit arrangement are combined, the analog / digital / converter outputs the binary value
  • This setting of the voltage threshold of the analog / digital / converter ensures that the tolerances of the components of the circuit arrangement have no influence on the Have measurement result and that the discharge characteristic of the time / voltage converter is only used in the linear range for time / voltage conversion.
  • This adjustment of the circuit arrangement is achieved in that the delay elements are equipped with different delay times.
  • a pulse to be measured for example the pulse edges or the pulse duration
  • Preliminary stage connected to which the measuring pulse is fed.
  • This precursor is for generating the start or stop pulse each composed of a comparator, dem'der measuring pulse and in each case an adjustable reference value is supplied, from a respective one connected to the output of the comparator differentiating element, and one each between the differentiating member and the delay element 'arranged gate .
  • the start or stop pulse necessary for the desired measurement is thus derived from the measurement pulse to be measured.
  • each gate circuit in the pre-stage is connected to an enable flip-flop which emits an enable signal when the gate circuit is to be open for the start or stop pulse and whose reset input is connected to the output of the associated delay element.
  • the time / voltage converter expediently consists of a differential amplifier, the inputs of which are connected to the outputs of the bistable flip-flop, of a discharge circuit with an adjustable capacitor which is connected to the one output of the differential amplifier for discharge with a constant current, and of one precharge circuit which can be switched off and which is connected to the discharge circuit for precharging the discharge circuit to a defined initial value.
  • a device under test PF is shown with an input E and an output A.
  • the test object PF is supplied with a test signal at the input E, which leads to a test object signal at its output A.
  • the temporal relationships of this test object signal at output A are measured with the aid of the circuit arrangement SH.
  • the circuit arrangement SH has two inputs ES1 and ES2.
  • the input ES1 can either be connected to the input E of the test object PF or to the output A of the test object.
  • the input ES2 of the circuit arrangement SH is connected to the output A of the device under test PF.
  • the input ES1 of the circuit arrangement SH is connected to the input E of the test object PF, it is possible, for example: to measure the time which elapses until the test signal at the input E DUT signal at output A occurs. If, on the other hand, the input ES1 is connected to the output A, the rise or fall time of the device under test or its pulse duration can be measured with the circuit arrangement SH.
  • the signal which is fed to the input ES is called the measuring pulse SN1
  • the signal which is fed to the input ES2 is called the measuring pulse SN2.
  • the measurement pulses SN1 and SN2 can be identical or different.
  • the measuring pulse SN1 is fed to the comparator CP1, which is also supplied with an adjustable reference voltage UR1.
  • the measuring pulse SN2 is fed to a comparator CP2, to which an adjustable reference voltage UR2 is also fed.
  • the comparators CP1, CP2 then output a signal when the measuring pulses SN1 or SN2 exceed or fall below the reference voltages UR1 or UR2.
  • Figure 4 shows the signal at output B of comparator CP1 and the signal at output C of comparator CP2. It has been assumed that the reference voltage UR1 corresponds to the value SW1 and the reference voltage UR2 to the value SW2.
  • the rise time TR or the fall time TF of the measuring pulse SN can thus be determined by appropriate selection of the edges of the signal at the output B or C of the comparators CP1 and CP2.
  • the pulse duration can also be measured by appropriately setting the reference voltages and selecting the comparator output edges.
  • the signals at the outputs B and C of the comparators CP1 and CP2 are each fed to a differentiator D G1 and DG2, which generate needle pulses SZ3 and SZ4 (FIG. 4) from the signals B and C.
  • a gate circuit TR and selection signals SKO, SK1 and SK2 the desired needle pulses SZ3 and SZ4 can be selected for measurement.
  • These selected needle pulses from the pulse train SZ3 and SZ4 are fed to a delay element VZ1 or VZ2.
  • the output of the delay element VZ1 is connected to the .set input of a bistable flip-flop FF, the output of the delay element VZ2 to its reset input.
  • the bistable flip-flop FF is released with the aid of an enable signal SF.
  • selection signals SKO, SK1 and SK2 can be such that e.g. Needle pulses at the output C of the comparator CP2 are diverted to the set input of the bistable flip-flop FF and accordingly needle pulses at the output B of the comparator CP1 are fed to the reset input of the bistable flip-flop FF. Or each needle pulse assigned to the rising edge or each needle pulse assigned to the falling edge can be selected at output B or C, etc.
  • the output pulse width of the bistable flip-flop FF corresponds to the time difference between the selected needle pulses, which have been fed to the set or reset input of the flip-flop FF.
  • this pulse width corresponding to the time to be measured is converted into a voltage proportional to the time.
  • the analog / digital / converter ADU a digital value is determined from the time, which is output at the output SA.
  • the analog / digital / converter ADU uses a signal EOC to indicate when the voltage has been converted into a binary value. This signal EOC is emitted at the output, but is also fed to the time-voltage converter ZSW at the same time. The time voltage converter ZSW is returned to its initial state by the signal EOC and thus prepared for the next measurement.
  • the time-voltage converter ZSW can be designed in such a way that a signal is output at the output ME if the measuring range is exceeded.
  • the reference voltages UR1 and UR2 can be set using digital-to-analog converters DAW1 and DAW2. These are supplied with the binary value SL1 or SL2, from which they then generate the reference voltage UR1 and UR2.
  • FIG. 2 and Figure 3 show a more detailed implementation of the circuit arrangement SH.
  • the comparator CP1 and the comparator CP2 have a non-inverting and an inverting output. Each output leads to an associated differentiator DG11 and DG12 for the comparator CP1 and DG21 and DG22 for the comparator CP2.
  • the outputs of the differentiators DG11 and DG12 are connected to a gate circuit, which consists of gate elements TR1 and TR2.
  • the differentiators DG21 and DG22 are connected to a gate circuit consisting of gate elements TR3 and TR4.
  • a positive spike corresponding to FIG 4 is given, when the rising edge of the measuring pulse SN, the reference voltage UR1. exceeds.
  • a positive needle pulse is emitted at the output of the differentiating element DG12 when the falling edge of the measuring pulse SN falls below the reference voltage UR1.
  • These needle pulses are summarized as signals SZ3 and SZ4 in Figure 4.
  • the output of the differentiating element DG11 or the output of the differentiating element DG12 can now be switched through to the output. Which gate link TR1 or TR2 is permeable, is determined using the selection signal SK1.
  • either the output of the differentiating element DG21 or the output of the differentiating element DG22 can be switched through to the output by the gate elements TR3 and TR4, depending on the selection signal SK2.
  • the outputs of the gate elements TR1 and TR2 are connected together and connected to the input of a delay element VZ1, the output of which leads to the set input S of the bistable flip-flop FF.
  • the outputs of the gate elements TR3 and TR4 are also connected together and connected to the input of a delay element VZ2, the output of which is connected to the reset input R of the bistable flip-flop FF.
  • the bistable flip-flop FF thus determines the time interval between the occurrence of the needle pulse at the output of the delay element VZ1 and the occurrence of the needle pulse at the output of the delay element VZ2.
  • the delay elements VZ1 and VZ2 are expediently designed such that the delay time of the delay element VZ2 is greater than that of the delay element VZ1. The advantage of this is explained below.
  • release flip-flops FG1 and FG2 are provided.
  • the release flip-flop FG1 is connected to the gate elements TR1 and TR2, the release flip-flop FG2 to the gate elements TR3 and TR4. If a measuring pulse SN is selected, the enable flip-flops FG1 and FG2 are set and thus the gate elements "TR1 to TR4 are enabled.
  • the reset input of the enable flip-flop FG1 is connected to the output of the delay element VZ1, the reset input of the enable flip-flop EG2 to the output of the delay element VZ2.
  • flip-flops FG1 and FG2 are reset and the gate elements TR1 to TR4 are blocked when the needle pulse selected by the gate elements TR appears at the output of the delay elements VZ1 and VZ2 and is thus fed to the bistable flip-flop FF.
  • the delay time of the delay elements VZ1 and VZ2 are selected such that the release flip-flops FG1 and FG2 are already reset before a needle pulse assigned to another measuring pulse SN can reach the gate elements TR.
  • the release flip-flops FG1 and FG2 and the bistable flip-flop FF are connected with their reset inputs R to a line for a reset pulse SR.
  • the flip-flops FG1 and FG2 and the bistable flip-flop FF are reset by pulses generated in the circuit arrangement.
  • Figure 2 shows an embodiment of the gate circuit TR according to Figure 1 such that a transition of the signal at the output A of the comparator CP1 to the delay element VZ2 and the signal at the output B of the comparator CP to the delay element VZ1 is not possible. Due to slight changes in the gate circuit TR, which are within the scope of the expert ability, a corresponding structure of the gate circuit is easily possible.
  • the outputs of the bistable flip-flop FF are connected to a differential amplifier DV.
  • One output of the differential amplifier DV is connected to a reference potential P1, for example ground.
  • the other output of the differential amplifier DV leads to a discharge circuit ET, which contains a capacitor CO.
  • the bistable flip-flop FF is not set, the differential amplifier DV is at the potential P1 connected and there is no discharge of the discharge circuit ET via the differential amplifier DV. If, on the other hand, the bistable flip-flop FF is set, the differential amplifier DV discharges the discharge circuit ET with a constant current. The duration of this unloading process is thus determined by the period of time that the bistable flip-flop FF is in the set state. However, this time corresponds to the time to be measured.
  • the discharge circuit ET is also connected to a precharge circuit AT, through which the discharge circuit ET is initially charged to a defined start, while the differential amplifier DV is connected to the potential P1.
  • the precharge circuit AT connects the discharge circuit ET to a voltage UV during this time.
  • the signal SZ3 occurs at the output of the gate elements TR1 and TR2
  • the precharge circuit AT is separated from the discharge circuit ET and the discharge circuit ET can only be influenced by the differential amplifier DV.
  • the precharge circuit AT is switched off or on with the aid of a bistable flip-flop KS1, to which the signal SZ3 is fed.
  • the flip-flop KS1 is only reset and the precharge circuit AT to the discharge circuit ET is switched on again when the conversion of the voltage output at the output of the discharge circuit ET into a binary value by the analog-digital converter ADU has ended, that is to say that it emits the signal EOC .
  • the differential amplifier DV and the discharge circuit ET are constructed in such a way that the capacitor CO contained in the discharge circuit ET is discharged with a constant current during the time during which the bistable flip-flop FF is set. This converts time into tension.
  • the unloading used Characteristic curve is shown in Figure 5.
  • the capacitor CO of the discharge circuit is precharged, for example, to +10 volts.
  • the differential amplifier DV switches over to the discharge circuit ET, the capacitor CO is discharged with constant current, ie the characteristic curve according to FIG. 5 transitions into the discharge region TE.
  • the voltage across the capacitor CO reaches zero volts. If the measurement is finished, this is indicated by the signal EOC, then the precharge circuit AT is connected again to the discharge circuit ET and the capacitor CO is recharged to +10 volts. A new time measurement can then begin again and thus a new discharge of the capacitor CO.
  • An operational amplifier JP1 is connected to the output of the discharge circuit ET and is connected in such a way that the discharge circuit ET is not loaded.
  • a reference voltage UR3 is fed to the operational amplifier OP1, which is set in such a way that work is carried out only in the linear region of the discharge characteristic.
  • the output of the operational amplifier OP1 is finally connected to the analog / digital / converter ADU, which generates a binary value at the output SA from the voltage output by the operational amplifier OP1.
  • FIG. 3 is still. a further flip-flop KS2 shown, to which the signal SZ4 is fed from the output of the gate elements TR3 and TR4 via a delay element VZ3. With this signal SZ4, the flip-flop KS2 is brought into its one state, in which it outputs the release signal SC for the analog / digital / converter ADC at the output.
  • the ADC analog / digital converter is only switched on when a needle pulse has occurred at the output of the gate elements TR3 and TR4. This needle impulse is caused by the delay approximately delayed VZ3 such that the analog / digital / converter ADU is not switched on too early.
  • the flip-flop KS2 can also be used to determine if the measuring range has been exceeded.
  • the output of the flip-flop KS1 is connected to a timing element Z1, the inverting input of which, together with the output of the delay element VZ3, is connected to an AND gate UD1, which leads to the input of the flip-flop KS2.
  • the output of the timing element Z1 is connected to a further timing element Z2, which is connected to a further AND element UD2.
  • the AND gate UD2 is still connected to the other output of the flip-flop KS2 and emits the measuring range exceeding signal ME at its output and continues to lead to the reset input of the flip-flop KS1.
  • the permissible measuring range is determined with the help of timer Z1. If the time between the occurrence of the signal SZ3 and the signal SZ4 becomes too long, then a signal will appear at the inverting output of the timing element Z1, which blocks the AND gate UD1, so that the flip-flop KS2 remains in the reset state. The result of this is that the AND gate UD2 is enabled and the measuring range exceeding signal ME can occur.
  • the output of the AND gate UD2 is still connected to the reset input of the bistable flip-flop KS1, so that it is also reset when the measuring range exceeding signal ME occurs. Furthermore, if the measuring range is exceeded, the release signal SC for the analog / digital / converter ADu is not generated, so that it is not released.
  • the output of the bistable flip-flop KS1, on which the signal SZ5 appears, is connected to the bistable flip-flop FF, so that this is reset when the signal SZ5 occurs. Then the evaluation process of the bistable flip-flop FF is ended in any case.
  • the time-to-voltage converter ZSW of FIG. 1 thus consists in any case of the differential amplifier DV, the discharge circuit ET, the precharge circuit AT, the bistable flip-flop KS1 and possibly the bistable flip-flop KS2, if a permissible measuring range is provided.
  • the inputs of the comparators CP1 and CP2, on which the measuring pulse occurs are short-circuited and the reference voltages UR1 and UR2 are set to the same value. Since the delay elements VZ1 and VZ2 have different values, the bistable flip-flop FF is set briefly. Consequently, the discharge circuit ET is briefly discharged from the differential amplifier DV. The reference voltage UR3. of the operational amplifier OP1 is now set so that this discharge is not yet evaluated by the analog / digital / converter ADC, that is to say the binary value at the output SA remains zero.
  • This measure ensures that component tolerances of the circuit arrangement do not influence the measurement result at the output of the analog / digital / converter ADC, and it also ensures that the start of the discharge characteristic (see FIG. 5) in which the characteristic is not linear is not used at the time / voltage conversion. Only the linear range of the discharge characteristic is used for the conversion.
  • the delay time of the timing element Z1 and the steepness of the discharge characteristic and thus the range in which a time / voltage conversion can be carried out must correspond to one another.
  • the discharge characteristic is selected by adjusting the capacitance of the capacitor CO such that the discharge characteristic according to FIG. 5 has just reached zero volts at the maximum time. Accordingly, the delay time of the timing element Z1 must also be selected.
  • the digital value SL of the reference voltage UR is transferred into a memory SP1 and into a memory SP2 when clock signals TS occur.
  • the memory SP1 is connected to the digital / analog / converter DAW1, the memory SP2 to the digital / analog / converter DAW2.
  • the binary value, which is in the memory SP, is converted by the digital / analog / converter DAW into a proportional current, from which the reference voltage UR1 or UR2 is generated via an operational amplifier.
  • the reference voltage UR1 and the measuring pulse SN1 or the reference voltage UR2 and the measuring pulse SN2 are fed to the comparators CP1 and CP2.
  • the outputs of the comparators CP1 and CP2 lead to the differentiators DG11, DG12 or DG21 and DG22.
  • the differentiators DG are implemented as short-circuited lines at the end, which are connected to a fixed potential. With the help of the short-circuited lines, symmetrical needle pulses are generated.
  • the gate elements TR1, TR2, TR3 and TR4 are implemented in FIG. 6 as NOR elements, to which the needle pulses, a selection signal SK and the output signal from the release flip-flop FG1 and FG2 are supplied.
  • the outputs of the gate elements TR1 and TR2 lead to the delay element VZ1, which is implemented as a line.
  • the outputs of the gate elements TR3 and TR4 lead to the delay element VZ2 implemented as a line.
  • the delay element VZ2 has a longer delay time than the delay element VZ1, e.g. at 5ns.
  • the signals supplied to the circuit arrangement have SR, SK, SF TTL levels, these are converted into ECL levels with the aid of TTL / ECL converters. It is also necessary that the enable signal SF is fed to a monoflop to generate a pulse after conversion into an ECL signal.
  • FIG. 7 shows an exact implementation of FIG. 3.
  • the signals SZ1 and SZ2 are fed to the differential amplifier DV.
  • a constant current source KSQ1 is connected to the emitters of the differential transistors T3 and T4, via which e.g. a constant current of 30 mA flows.
  • the constant current flows either via the differential transistor T3 to the potential P1 or via the differential transistor T4 to the discharge circuit ET.
  • the discharge circuit ET essentially consists of the capacitor CO, which consists of a capacitor with a fixed capacitance and a capacitor with a variable capacitance.
  • the differential amplifier DV is connected to the connection point VP, specifically via a transistor T10 in the basic circuit. This transistor compensates for the Miller effect of the differential transistor T4.
  • AndLe discharge circuit ET is connected to the precharge circuit AT, which consists of the constant current source KSQ2, which can be switched off via the transistor T1.
  • the constant current source KSQ2 is connected to the connection point VP via diodes D1, D2, D3. It is controlled via an operational amplifier OP2, at the inverting input of which the voltage UV is present.
  • the non-inverting input of the operational amplifier OP2 is connected to the connection point VP. This feedback causes the voltage at connection point VP to be as long as the constant current source KSQ2 is switched on, is approximately + 10 volts.
  • the constant current source KSQ2 is switched off via the transistor T1, the base of which is connected to a further differential amplifier DV1.
  • This differential amplifier DV1 is connected to the bistable flip-flop KS1, the. the signal SZ3 is supplied.
  • the transistor T1 is turned on via the differential amplifier DV1, so that there is approximately ground potential at the collector of the transistor T2 of the constant current source KSQ2.
  • the diodes D1 to D3 are operated in order to keep the total capacitance as small as possible.
  • the signal SZ4 is applied to the input of the bistable flip-flop KS2 via a delay element VZ3 implemented as a line.
  • the output of the bistable flip-flop KS1 is also present at this input via the timing element Z1, which is implemented as a monoflop.
  • the timing element Z2 is also implemented as a monostable multivibrator. The interaction of the bistable flip-flop KS2 with the timing elements Z1 and Z2 and with the delay line VZ3 has already been described above.
  • analog / digital / converter ADU processes TTL signals, while the remaining circuit part of FIG. 7 generates ECL signals.
  • ECL / TTL converters are again required in the lines for the measuring range exceeding signal ME, for the enable signal SC and for the signal EOC.
  • Monostable multivibrators are also inserted to generate the pulses required for operation.
  • a commercially available module can be used as the analog / digital / converter ADU. This also applies to the digital / analog / converters DAW1 and DAW2, the operational amplifiers OP and the comparators CP. The remaining components of FIGS. 4 and 7, which are not described, are used in a known manner for the necessary wiring of the individual components used.
  • Y is a voltage of 0.8V.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Analogue/Digital Conversion (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
EP84110185A 1983-09-08 1984-08-27 Montage pour la mesure d'intervalles de temps courts Expired EP0141122B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT84110185T ATE34852T1 (de) 1983-09-08 1984-08-27 Schaltungsanordnung zur messung kurzer zeit.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3332484 1983-09-08
DE19833332484 DE3332484A1 (de) 1983-09-08 1983-09-08 Schaltungsanordnung zur messung kurzer zeiten

Publications (2)

Publication Number Publication Date
EP0141122A1 true EP0141122A1 (fr) 1985-05-15
EP0141122B1 EP0141122B1 (fr) 1988-06-01

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EP84110185A Expired EP0141122B1 (fr) 1983-09-08 1984-08-27 Montage pour la mesure d'intervalles de temps courts

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EP (1) EP0141122B1 (fr)
AT (1) ATE34852T1 (fr)
DE (2) DE3332484A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2540730A (en) * 2015-05-11 2017-02-01 Thermo Fisher Scient (Bremen) Gmbh Time interval management

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3553582A (en) * 1967-01-24 1971-01-05 Onera (Off Nat Aerospatiale) Method and apparatus for measuring a time interval
US3735261A (en) * 1971-06-07 1973-05-22 Northrop Corp Pulse analyzer
EP0051531A1 (fr) * 1980-10-31 1982-05-12 Electronique Serge Dassault Appareillage pour la datation précise d'un évènement par rapport à une référence de temps

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3553582A (en) * 1967-01-24 1971-01-05 Onera (Off Nat Aerospatiale) Method and apparatus for measuring a time interval
US3735261A (en) * 1971-06-07 1973-05-22 Northrop Corp Pulse analyzer
EP0051531A1 (fr) * 1980-10-31 1982-05-12 Electronique Serge Dassault Appareillage pour la datation précise d'un évènement par rapport à une référence de temps

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, Band 10, Nr. 12, Mai 1968, Seiten 1888-1890, New York, US; E.H. MILLHAM et al.: "Propagation delay and pulse width tester" *
INSTRUMENTS AND EXPERIMENTAL TECHNIQUES, Band 23, Nr. 5, Teil 1, September/Oktober 1980, Seiten 1155-1157, Plenum Publishing Corp., New York, US; YU.K. AKIMOV et al.: "Nanosecond time-amplitude converter" *
NUCLEAR INSTRUMENTS AND METHODS, Band 78, Nr. 1, 1. Februar 1970, Seiten 109-114, North-Holland Publishing Co., NL; N. BALAUX u.a.: "Convertisseur temps-amplitude de haute resolution" *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2540730A (en) * 2015-05-11 2017-02-01 Thermo Fisher Scient (Bremen) Gmbh Time interval management
GB2540730B (en) * 2015-05-11 2017-09-13 Thermo Fisher Scient (Bremen) Gmbh Time interval measurement
US9947525B2 (en) 2015-05-11 2018-04-17 Thermo Fisher Scientific (Bremen) Gmbh Time interval measurement

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Publication number Publication date
EP0141122B1 (fr) 1988-06-01
DE3332484A1 (de) 1985-03-28
ATE34852T1 (de) 1988-06-15
DE3471773D1 (en) 1988-07-07

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