EP0117344B1 - Memory system - Google Patents

Memory system Download PDF

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Publication number
EP0117344B1
EP0117344B1 EP83307251A EP83307251A EP0117344B1 EP 0117344 B1 EP0117344 B1 EP 0117344B1 EP 83307251 A EP83307251 A EP 83307251A EP 83307251 A EP83307251 A EP 83307251A EP 0117344 B1 EP0117344 B1 EP 0117344B1
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EP
European Patent Office
Prior art keywords
data
memory
address
row
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP83307251A
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German (de)
English (en)
French (fr)
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EP0117344A3 (en
EP0117344A2 (en
Inventor
Hisao Ishizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
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NEC Corp
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Publication date
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Publication of EP0117344A2 publication Critical patent/EP0117344A2/en
Publication of EP0117344A3 publication Critical patent/EP0117344A3/en
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Publication of EP0117344B1 publication Critical patent/EP0117344B1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/903—Querying
    • G06F16/90335—Query processing
    • G06F16/90339—Query processing by using parallel associative memories or content-addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Definitions

  • the present invention relates to a memory system, and more particularly, to an improved memory access circuit (addressing circuit) used in a digital data processing system in which a large amount of data are handled.
  • a memory is invariably employed in a digital data processing. Hence, for making the digital data processing higher in speed, it is exceedingly effective to reduce the access time (read time and write time) for the memory.
  • the reduction of the memory access time is particularly effective in a system that handles a large amount of data, such as a speech recognition system and a picture information processing system.
  • the dynamic pattern matching (DP matching) method is generally employed. This method is such that feature vector data extracted from an input speech information to be recognized are employed as input patterns, each of which is compared with reference patterns .(standard patterns) of reference vector data previously registered to find a standard pattern which is highest in the standard patterns in coincidence degree with the input pattern thereby to recognize the input speech.
  • the input patterns and the reference patterns are generally represented as a time series of feature vectors of speech.
  • the feature vector includes, as its components, intensities in various frequency bands obtained by the speech frequency analysis and parameters obtained by a linear predictive analysis.
  • For the pattern matching it is required to obtain a distance between an input pattern vector a at a point of time i and a standard pattern vector b j at a point of time j, i.e. d ⁇ , j (e.g., the sum total of the differences between the various vector components). Therefore, for obtaining one distance d i,j' it is necessary to read out two data trains a,, b ; from a memory and feed these data trains into an arithmetic device. Since pattern data are generally large-capacity data (assuming that the sound voiced for one second requires eight kilobits, the sound voiced for 100 seconds requires 800 kilobits), memory devices independent of each other are employed for storing input patterns and storing standard patterns, respectively.
  • the time required from the point of time when necessary pattern data are read out from the respective memory devices by memory access operations until the point of time when these pattern data are fed into an arithmetic device is much longer than an execution time of the arithmetic device required to execute a distance computation therein.
  • at least two data are always required for executing the distance computation.
  • the arithmetic device cannot start the computation for obtaining a distance value until these two data are fed therein, so that a data processing of a prior art is exceedingly low in efficiency.
  • a major cause for the low efficiency is that the conventional memory system cannot overlap the cycle for reading out data from the memory with the cycle for computing a distance value with each other. Moreover, if a RAM having a working area is used as a memory for storing the input pattern and the reference pattern, another cycle for writing next new data to be used by the arithmetic device into the RAM is required, so that the data processing speed becomes lower.
  • the speech recognition processing cannot be put to practical use if the response time is long from the point of time when speech is fed until the point of time when the result of recognition is delivered, the data processing must be completed within a short period of time.
  • the number of input patterns is larger, matching takes a longer time, and as the recognition data processing speed is lower, the number of recognized words is smaller. Accordingly, a memory access speed is a significant factor to process data efficiently.
  • the arithmetic device must wait for data for long time as described above, so that a high-speed processing can not be obtained.
  • the manufacture of a memory device having a high access speed has limitation in the device process technique.
  • the apparent access time must be reduced by improving both read-out and writing circuits in the memory system.
  • the circuit configuration is complicated by this improvement, it is difficult to form the memory device on an integrated semiconductor chip, so that a plurality of chips must be combined to form the memory system. In such a case, the critical path among the chips becomes long; hence, the memory access time becomes long. Accordingly, peripheral circuits of a memory array must be simple as much as possible.
  • EP-A-0 057 755 there is described a microcomputer system in which the searching of multi-byte characteristic blocks stored in the working storage of the system is facilitated by employing comparison stages having a read- write store in which bytes of one block of characteristics are stored with the same relative address; a search mode address control unit enabling all of the bytes of a block of characteristics to be read out simultaneously from the data file storage zone of the read write store.
  • the present invention is defined in Claim 1.
  • An embodiment of the present invention to be described below includes; first and second memory blocks; first and second arithmetic devices; an addressing means for supplying a first address commonly to the first and second memory blocks; means for simultaneously reading out first and second data from the first memory block by the first address during a one memory access period; means for reading a third data from the second memory block by the first address during the one memory access period simultaneously with the reading out of the first and second data; and means for supplying the first and third data to the first arithmetic device and simultaneously supplying the second and third data to the second arithmetic device.
  • Such a memory system can be provided by the following arrangement:
  • the memory system comprises: at least two memory blocks A, B; a first addressing means for writing data into a first memory block A; a second addressing means for writing data into a second memory block B; a third addressing means for reading data in common out of both the first and the second memory blocks A and B; and a data output means for simultaneously delivering data at two or more address locations of the first memory block A as well as delivering data at one or more address locations of the second memory block B in the same period, wherein one data stored at the memory location of the first memory block A specified by the read address and the other data stored at the other memory location of the first memory block A corresponding to the other address different from the read address are simultaneously delivered by the data output means, while a data of the memory block B is also simultaneously delivered in response to the third addressing means and the second addressing means.
  • the memory system in of the present arrangement can be well applied to the picture processing field or data processing field in which a large amount of data are handled, in addition to the above-mentioned speech processing field.
  • Figure 1 is a block diagram of an essential part of a memory system in accordance with an embodiment of the present invention.
  • the memory system shown in Figure 1 includes: a memory array 1 constituted by N rows and M columns; a memory array 2 constituted by two rows and M columns; a write addressing circuit 3 for the memory array 1; a write addressing circuit 4 for the memory array 2; a read addressing circuit 5 in common to both the memory arrays 1, 2; registers 6, 7 for storing two data delivered from the memory array 1, respectively; and a register 8 for storing the data delivered from the memory array 2.
  • the read addressing circuit 5 is constituted by a row specifying section and a column specifying section.
  • the column designation in the memory arrays 1, 2 is effected by the column specifying section of the circuit 5.
  • the row designation in the memory arrays 1, 2 in which data to be delivered to the registers 6, 7, 8, respectively, are stored is effected as follows: In the register 6, the data on the row specified by the row specifying section of the read addressing circuit 5 is read out and set; in the register 7, the data on the row selected by an address value obtained adding one to the address value specified by the row specifying section of the read addressing circuit 5; and in the register 8, the data on either the first or second row of the memory array 2 which is specified by the row specifying section of the write addressing circuit 4 for the memory array 2.
  • the row specifying section of the write addressing circuit 4 when the row specifying section of the write addressing circuit 4 is an address value "1", the data on the second row is set in the register 8; when the row specifying section is an address value "2", the data on the first row is set therein.
  • the row specifying section of the read addressing circuit 5 indicates an address value "N"
  • the row the data on which is to be delivered to the register 7 returns to the first row.
  • the row specifying sections of the two addressing circuits 3, 5 should be modulo N counters, respectively, while the row specifying section of the write addressing circuit 4 should be a modulo 2 counter.
  • a memory array 10 (corresponding to the memory array 1 shown in Figure 1) is divided into, for example, four banks (blocks), from each of which an output line is led out in common.
  • the low-order bits of an address set (value) in an address register 12 are decoded in a decoder 15 to specify these illustrated four banks in common.
  • the read-out four data are fed into two multiplexors 17, 18 placed at the output stage in the memory system in common to each other.
  • the multiplexor 17 is adapted to select one of the four data according to the value of two high-order bits of the address register 12 and set the selected data in an output register 13. Moreover, the two high-order bit address is incremented by one by means of a +1 adder 16 and supplied to the multiplexor 18. According to the value incremented by one, the multiplexor 18 selects one of the four banks and transfer the data in the selected bank to an output register 14. As a result, two data at memory locations physically different from each other are simultaneously accessed by only one addressing.
  • the multiplexor 17 specifies the banks 8 1 , B 2 . B 3 . B 4 . respectively.
  • the outputs of the +1 adder 16 are (0, 1), (1, 0), (1, 1), (0, 0), respectively; therefore, the multiplexor 18 selects the banks B 2 , B 3 , 8 4 , 8 1 , respectively.
  • a pair of data can be simultaneously read out with a single addressing by constituting the read addressing circuit (represented by a reference numeral 5 in Figure 1) in which the address register 12, a decoder 15, the +1 adder 16 and the multiplexors 17, 18 are included as shown in Figure 2 and dividing the memory array 10 into a plurality of blocks. Accordingly, if one of a set of two data is an input pattern, while the other is a standard (reference) pattern, then it is possible to read out two data employed in a distance calculating operation within a period of time required for only one memory access.
  • the memory array 2 is added as shown in Figure 1, the following memory system can be obtained: Input patterns are stored in the memory array 1, while standard patterns are stored in the memory array 2.
  • the input pattern memory array 1 and the standard pattern memory array 2 are accessed by the mutual read addressing circuit 5. Therefore, even if only one input pattern is read out from the memory array 1 at a time, since an input pattern and a standard pattern as a set are simultaneously read out, the time required for the preparation of data for the distance calculating operation is reduced to about a half of the time need conventionally.
  • the memory array 1 and the memory array 2 are arranged so as to have the same number of columns, an operand (input pattern) and an operand (standard pattern) employed for the identification of the former operand can be accessed by the use of the same address, and addressing for these two data is remarkably simple.
  • a speech data to be recognized is transferred through input terminal to a memory 33 in which a standard pattern data to be compared with the speech data is stored.
  • a processor 34 reads the speech data (input pattern vector) and the standard pattern data (standard pattern vector) out of the memory 33, respectively, and transfers the input pattern data and the standard pattern data to a memory array 21 and a memory array 22, respectively, by controlling a selector 35.
  • the address is set so that the contents of a write addressing circuit 23 specify the first row in the first column (I 1-1 ) of a memory array 21, and a first component of an input pattern vector a j - r is written at the specified location. It is assumed that the input pattern vector A j - r has M components.
  • the column specifying section of the write addressing circuit 23 is incremented by one to specify a location I 1-2 , at which a second component, subsequent to the first component, is written. By the repetition of this operation, the M components of the input pattern vector a j - r are all written in the first row in the memory array 21.
  • the row specifying section of the write addressing circuit 23 is incremented by one, and the column specifying section thereof is made to specify the first column.
  • the address refers to a location 1 2 - 1 (the second row in the first column).
  • the address is set so that the contents of a write addressing circuit 24 specify the first row in the first column (S 1-1 ) of a memory array 22, and a first component of the standard pattern vector b j is written at the location.
  • the column specifying section of the write addressing circuit 24 is incremented by one to write a second component of the standard pattern vector b j at a location in a subsequent column (S 1 - 2 ).
  • the data bout the standard pattern vector b j are all written in the first row (S 1-1 to S 1-M ) of the memory array 22.
  • the write addressing circuit 23 Upon completion of the above write processing, the write addressing circuit 23 is holding such an address as specifing the (2r+1)th row in the M column (I( 2r+1)-M ), while the write addressing circuit 24 is holding such an address as specifying the first row in the M column (S 1-M ). Therefore, the row specifying section is incremented by one, and the column specifying section is made to indicate "1". As a result, the contents of the address specifying circuit 23 specify 1 (2r+2)' while the contents of the write addressing circuit 24 specify S 2 - 1 . On the other hand, in the reading mode, the address is set so that the read addressing circuit 25 specifies the first row in the first column (1 1 - 1 ).
  • the first components of the input pattern vectors a j - r , a j - r+1 are simultaneously set in registers 26, 27, respectively, and the first component of the standard pattern vector b j (i.e. the data at S 1 - 1 ) is set in a register 28 at the same time.
  • the second components of the pattern vectors a j -,, a j-r+1 , b j i.e., the data at 1 1 - 2 , 1 2 - 2 , S 1-2 , respectively
  • the registers 26, 27, 28, respectively More specifically, every time a reading operation is executed, it is possible to simultaneously obtain three data required for effecting two distance calculating operations.
  • a distance calculating device 29 coupled to the registers 26, 28 and a distance calculating device 30 coupled to the registers 27, 28 are provided for conducting the execution of the calculating devices and the operation of reading out data from the memory arrays 21, 22 in synchronism with each other, the distance d j-r, j and the distance d j-r+1, j can be simultaneously obtained by repeating the processing operation M times.
  • the address of the row specifying section of the read addressing circuit 25 is incremented by two, while the address of the column specifying section thereof is incremented by one.
  • the distance d j-r+2, j and the distance d j-r-3, j can be simultaneously obtained by repeating the processing operation M times similarly to the above. By the repetition of the above processing operation, it is possible to obtain the following distances:
  • the data about the input pattern vector a j+r+1 are all stored in the (2r+2)th column in the memory array 21.
  • the first component of the standard pattern vector b j+ is written at the location S 2-1 in the memory array 22.
  • the data about the standard pattern vector b j+1 are all stored in the second column (S 2 - 1 to S 2-M ) in the memory array 22. Since the regions for writing data in the memory arrays 21, 22 and the region for reading out data therefrom are not overlapped with each other, the writing and reading operations can be carried out independently of each other.
  • the time T A required for effecting operations for calculating distances between a standard pattern at one point of time and a series of input patterns is expressed as follows:
  • the time T B required for writing data in the memory arrays 21, 22 for carrying out operations for calculating the distances between a standard pattern at a subsequent point of time and a series of input patterns is expressed as follows: If the condition of T, T, is satisfied, it is possible to constantly obtain data required for the distance calculating unit by executing the reading and writing operations in parallel with each other, so that waste is completely eliminated.
  • the memory access time can be greatly reduced, so that the arithmetic unit can effect an efficient processing operation. Accordingly, the memory system can well satisfy the high-speed properties required for the recognition processing.
  • the memory array 2 has only one data output means in the above- described embodiment, it is easy to improve such that the memory array 2 is constituted by four rows and M columns and provided with two data output means. In such a case, if the arrangement is such that components of the standard pattern vectors b j and b j+1 can be obtained through the two data output means, then it is also possible to obtain four distances by repeating the reading and calculating operations M times. Moreover, it will be obvious that three distances can be obtained by adding another data output means to the memory array 21 in accordance with the above embodiment.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Linguistics (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
  • Complex Calculations (AREA)
EP83307251A 1982-11-26 1983-11-28 Memory system Expired EP0117344B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57206992A JPS5998387A (ja) 1982-11-26 1982-11-26 メモリ回路
JP206992/82 1982-11-26

Publications (3)

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EP0117344A2 EP0117344A2 (en) 1984-09-05
EP0117344A3 EP0117344A3 (en) 1987-02-04
EP0117344B1 true EP0117344B1 (en) 1989-04-19

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EP83307251A Expired EP0117344B1 (en) 1982-11-26 1983-11-28 Memory system

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US (1) US4587637A (ru)
EP (1) EP0117344B1 (ru)
JP (1) JPS5998387A (ru)
DE (1) DE3379695D1 (ru)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4663742A (en) * 1984-10-30 1987-05-05 International Business Machines Corporation Directory memory system having simultaneous write, compare and bypass capabilites
US5237532A (en) * 1986-06-30 1993-08-17 Kabushiki Kaisha Toshiba Serially-accessed type memory device for providing an interleaved data read operation
US5167018A (en) * 1986-09-24 1992-11-24 Daikin Industries, Ltd. Polygon-filling apparatus
JPS6381688A (ja) * 1986-09-26 1988-04-12 Hitachi Ltd 半導体記憶装置
US4751641A (en) * 1986-12-22 1988-06-14 Ncr Corporation Method and apparatus for storing data to facilitate price look-up
US4903197A (en) * 1987-02-27 1990-02-20 Bull Hn Information Systems Inc. Memory bank selection arrangement generating first bits identifying a bank of memory and second bits addressing identified bank
JPH0612609B2 (ja) * 1987-03-27 1994-02-16 株式会社東芝 半導体メモリ
US4939692A (en) * 1988-09-15 1990-07-03 Intel Corporation Read-only memory for microprocessor systems having shared address/data lines
JP2950427B2 (ja) * 1989-01-13 1999-09-20 株式会社東芝 レジスタバンク回路
KR930007185B1 (ko) * 1989-01-13 1993-07-31 가부시키가이샤 도시바 레지스터뱅크회로
US5301350A (en) * 1989-10-10 1994-04-05 Unisys Corporation Real time storage/retrieval subsystem for document processing in banking operations
JPH0452760A (ja) * 1990-06-14 1992-02-20 Koufu Nippon Denki Kk ベクトル処理装置
JPH04181373A (ja) * 1990-11-15 1992-06-29 Koufu Nippon Denki Kk ベクトル処理装置
JPH04181374A (ja) * 1990-11-15 1992-06-29 Koufu Nippon Denki Kk ベクトル処理装置
US5359557A (en) * 1992-12-04 1994-10-25 International Business Machines Corporation Dual-port array with storage redundancy having a cross-write operation
US5544338A (en) * 1992-12-31 1996-08-06 International Business Machines Corporation Apparatus and method for raster generation from sparse area array output
US5630063A (en) * 1994-04-28 1997-05-13 Rockwell International Corporation Data distribution system for multi-processor memories using simultaneous data transfer without processor intervention
JP2964881B2 (ja) * 1994-09-20 1999-10-18 日本電気株式会社 音声認識装置
JP2980026B2 (ja) * 1996-05-30 1999-11-22 日本電気株式会社 音声認識装置
JPH10275460A (ja) * 1997-04-01 1998-10-13 Sega Enterp Ltd メモリ装置及びこれを用いた画像処理装置
WO2002103677A1 (en) * 2001-06-19 2002-12-27 Intel Corporation Method of employing prefetch instructions in speech recognition
CN111488297B (zh) * 2020-04-02 2023-04-14 杭州迪普科技股份有限公司 用于访问寄存器的方法、装置、电子设备及可读介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761898A (en) * 1971-03-05 1973-09-25 Raytheon Co Random access memory
NL7103773A (ru) * 1971-03-20 1972-09-22
JPS5529803A (en) * 1978-07-18 1980-03-03 Nippon Electric Co Continuous voice discriminating device
US4419746A (en) * 1980-10-14 1983-12-06 Texas Instruments Incorporated Multiple pointer memory system
JPS5771589A (en) * 1980-10-20 1982-05-04 Sanyo Electric Co Ltd Memory exclusively used for read-out of semiconductor
DE3104941A1 (de) * 1981-02-11 1982-08-26 Siemens AG, 1000 Berlin und 8000 München Mikrorechnersystem zum raschen auffinden von kennzeichenbloecken

Also Published As

Publication number Publication date
JPS6252392B2 (ru) 1987-11-05
JPS5998387A (ja) 1984-06-06
EP0117344A3 (en) 1987-02-04
EP0117344A2 (en) 1984-09-05
US4587637A (en) 1986-05-06
DE3379695D1 (en) 1989-05-24

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