EP0088202B1 - Générateur de séquence d'adresses de mémoire - Google Patents

Générateur de séquence d'adresses de mémoire Download PDF

Info

Publication number
EP0088202B1
EP0088202B1 EP83100018A EP83100018A EP0088202B1 EP 0088202 B1 EP0088202 B1 EP 0088202B1 EP 83100018 A EP83100018 A EP 83100018A EP 83100018 A EP83100018 A EP 83100018A EP 0088202 B1 EP0088202 B1 EP 0088202B1
Authority
EP
European Patent Office
Prior art keywords
sequence
address
memory
binary
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP83100018A
Other languages
German (de)
English (en)
Other versions
EP0088202A3 (en
EP0088202A2 (fr
Inventor
Robert Edwin Jones
Donald Hubert Wood
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0088202A2 publication Critical patent/EP0088202A2/fr
Publication of EP0088202A3 publication Critical patent/EP0088202A3/en
Application granted granted Critical
Publication of EP0088202B1 publication Critical patent/EP0088202B1/fr
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31813—Test pattern generators

Definitions

  • This invention relates to a memory address sequence generator and more specifically to logic circuits for producing any one of a plurality of sequences of addresses for use with an apparatus for testing the operation of a memory.
  • test patterns used such as galloping patterns and diagonal patterns per se are known e.g. from US patent US-A-4,300,234.
  • VLSI circuit memories are subject to various failure modes which are set forth in tabular form and correlated with the various test protocols designed to test for the faults, some of which protocols will detect more than one fault.
  • the relativity of the test times of each of the test protocols is set forth as a ratio compared with the longest test, wherein the test time factor is 2(2N 2 +N), where N is the number of test cells.
  • the article computes the number of test iterations as 67 117 056 cycle points.
  • address sequences is one of the principal areas that have heretofore required frequent repetitive access to a memory to determine which cells in the memory should be next addressed for testing.
  • examination of the address sequence of the various protocols reveals that the sequences obey fixed arithmetic progressions, which, although differing among the various test protocols obey fixed rules within any one protocol. This recommends the use of combinations of logic elements which can be preconditioned to generate the required address sequences with a minimum of inputs and controls from the controlling computer's memory.
  • Yet another object is provide an address generating apparatus having a plurality of identical combinations of logic instrumentalities which are operative in combination to selectively produce address sequences for the whole or any selected area of a matrix.
  • the memories for which this apparatus is particularly adapted to address for test purposes are two-dimensional matrix memories.
  • each cell or memory position can be defined by the coordinates of its position in the matrix.
  • the memory matrix size is usually 2"x2"' where n and m are integers.
  • the X and Y addresses may conveniently be encoded by means of 2"-1 and 2'-l binary bits.
  • the addresses of the cells in a row of the matrix run from 0 to 2"-1, and the column cells from 0 to 2m-1.
  • memories commonly called 2K, 4K, 16K, etc. actually contain 2", 2 12 , and 2 14 cells, respectively. These may be organized in a square or rectangular matrix so long as the both dimensions are an integral power of two.
  • These addresses may be incremented or decremented by any desired fixed amount. They may be masked to prevent an address from exceeding a predetermined value, and if desired, repeating the sequence of values up to the value of the mask. Addresses may be offset by the addition of a constant to the sequence of base addresses so as to be direct the testing to an area of the memory displaced from the origin by the value of the constant. Also the testing may be so controlled to alternate between cells obeying one sequence and cells obeying a second sequence.
  • Masking involves combining each binary bit in the desired address in a logical AND function with the binary bits representing that binary address beyond which further addressing is blocked. For example if it is desired to limit addresses to no greater hhan 111(7) the addresses from 000 through 111 would be reproduced without change. However, when the next count of 1000 is ANDED bit-by-bit with 0111, the derived address will be 000 and the sequence 000 through 111 will be repeated for all binary values greater than 1000.
  • a further relationship which is exploited is the so-called "home” and "away” address.
  • This permits a testing sequence wherein one memory cell (the “home” cell) may be repeatedly interrogated alternating with a succession of "away” cells. The "home” cell is then advanced to a new cell and alternately tested with a new succession of "away” cells.
  • the succession of both the "home” and “away” cells may be either an ascending or descending series which may be incremented by any integral amount. If the "home” cell lies in the middle of an array, the succession of "away” cells will on occasion include cell addresses greater than the memory capacity. Through masking the "away” cell, addresses will increase to the maximum return to zero and then approach the "home” cell by means of an increasing succession of lesser addresses.
  • a final relationship is the "offset" feature.
  • the "offset” feature also permit the alternating testing of a succession of cells occupying the same relative geometric position in two different areas of a memory. This is usually reserved for exercising sense amplifiers which are shared by a plurality of memory cells.
  • the specific test protocol chosen for any given memory is dictated by the potential fault sought to be detected and the size and geometry, including the disposition of sense amplifiers, of the memory.
  • the address generator now to be described is preset with the necessary parameters of a constant for changing the address, whether the constant is to be effective additively or subtractively (increment/decrement), the starting point for the numerical series (base address), and the selection of the area to be tested.
  • FIG. 1 four identical address generators A, B, C and D are shown schematically, each of which is constructed in accordance with the component arrangement of Fig. 2.
  • Inputs to the A, B, C and D units are multi-wire cables 90A, 90B, 90C and 90D, the individual wires, or multi-bit cables, of which are identified in detail in Fig. 2.
  • the A and B units are used to generate the X addresses, and the C and D units are used to generate the Y addresses.
  • the A and C units produce the "home” addresses and the B and D units produce the "away” addresses.
  • Selection of the "home” or “away” addresses is controlled by the selection units 50 (for X) and 60 (for Y) under control of an appropriately timed potential on line 55.
  • Each of the selection units, 50 or 60 is the solid state equivalent of a 16 pole double-throw relay which has the capability of selecting 16 bits of a "home” or “away” address in the X and Y directions.
  • any cell in a memory can be accessed in a desired sequence.
  • the units 61, 62, 63 and 64 consist of four four-bit buffer storage units which when strobed with an appropriate timing pulse are receptive to receive and store a total of 16 bits of binary data and to produce a corresponding composite 16 bit output.
  • Typical of these is TI type S.N. 72S175.
  • Units 67 and 68 contain four arithmetic logic units (ALU's) like TI type S.N. 74S381 cascaded to provide a 16 bit capacity with carry propagation.
  • ALU's may be conditioned for any one of eight logic functions by combinations of control potentials on three input lines (e.g. lines 69 and 70). In the application of this invention only the add function is employed.
  • the unit 71 is an EXCLUSIVE OR logic unit composed of four four-bit units such as TL type 74S86.
  • the individual bit orders are individually combined so that non-alike inputs to the order will yield a "1" output on that order and like inputs will yield a "0" output.
  • the gate 72 is similarly structured to provide sixteen outputs as the logical AND function of sixteen pairs of inputs. It is typically constructed of four TI type S.N. 74S08.
  • the selectors 50 and 51 are fabricated from 4 each of TI type S.N. 74S157.
  • the cables 90A through 90D consist of the cables 69, 70, 81, 82, 83, 84 and wires 65 and 66 grouped under the bracketed designation 90 in Fig. 2.
  • the encircled number is the number of wires within the respective cables.
  • the capacity of the address generator in the preferred embodiment is 16X and 16Y address bits, which if fully utilized could address a memory of 2 16 X 2 16 bits, if square. Through masking, any memory of smaller capacity or non-square matrix atray can be addressed. For example, a 64K (65 536) by 1 bit memory (improbable) would utilize the total X capacity but only one Y address.
  • addresses run from 0 to 2 n - I where n is an integer.
  • the buffer stores 63 and 64 and the arithmetic logic unit 67 generate the sequence of base addresses independent of memory size. In essence it is a counter which counts in increments of an integral number, set as a constant into the buffer store 63, whenever a clock timing pulse is entered to strobe the buffer store to receive an input. If, for example, buffer store 63 is present to a binary value of 1, the ALU 67 will immediately manifest a binary 1 in the low order and all zeros in the fifteen higher orders.
  • the buffer store is initially set to all ones, which when added to the single one in ALU 67 produces a sum of all zeroes.
  • a clock pulse on line 65 strobes the buffer store 64 to receive the all zeroes from the ALU 67 which then adds the constant "1" from buffer store 63 to the "0" in buffer store 64 to produce a base address of 1.
  • the value of the number in the ALU 67 may be increased by the constant amount stored in buffer store 63.
  • the incrementing occurs only when the clock pulse on line 65 allows the output from the ALU 67 to be entered in the buffer store 64.
  • This combination of the ALU 67 and buffer store 64 is the equivalent of a counter which can be preset to count by any desired increment.
  • Fig. 2 units interconnected as shown in Fig. 1.
  • the timing pulses applied to the 65A, 65B, 65C or 65D wire in cables 90A, 90B, 90C or 90D will differ in their frequency of occurence as a function of the relative rates at which the X-home, X-away, Y-home and Y-away addresses are to be altered.
  • the 16-bit output from ALU 67 is applied as one input to a 16-position EXCLUSIVE OR gate 71 which receives a second 16-bit input on cable 83 to cause the output of gate 71 to be incremented or decremented as explained above in the section entitled "Decrementing".
  • the incremented or decremented binary values are combined bit by bit (16 bits) with the masking bits from buffer store 62 and present by entry on cable 82 into each of the A, B, C and D units.
  • the manner of masking has been explained above under that section heading.
  • the ALU 68 performs this addition under control of combinations of potentials on cable 70.
  • the specific combination for adding for the chosen ALU's is 011.
  • the 16-bit output from ALU 68 is the X (home/away) or Y (home/away) address employed to access the memory.
  • each successive cell becomes a "home” cell.
  • the "away” cells are a succession of cells starting with the first cell in the array and ending with the last cell in the array.
  • the "home” and “away” cells are tested in alternate succession and the operative "home” cell is actually tested twice, once as a "home” cell and again as an “away” cell. This simplifies the circuitry and controls and provides the same testing integrity as the more complicated "home” and "away” sequences described in the foregoing referenced publication.
  • the number of "away” cells is a constant and equal to the number of cells in the array.
  • the succession of "away” cells is 0 through 127, which in this instance actually test cell 0 twice.
  • the "home” and “away” ALU's 67A, 67B, 67C and 67D are initially preset to begin addressing at the 0-0 origin.
  • the cables 83A through 83D carry all 0's to effect incrementing.
  • Cables 69A through 69D and 70A through 70D control the ALU's to add.
  • Mask registers 62A and 62C are set to a value of 0111 (the maximum X address), and the registers 62B and 62D are set to 01111 (the maximum Y-address).
  • External counters counting the X-home and away cycles are preset to 0111.
  • the counters for Y-home and away are preset to 01111. Every interrogation cycle the Y-away counter is decremented by one count. When it recycles from 0 to its preset value of 15 it decrements the X-away counter by one count. This advances the interrogation downward in a column to the bottom, steps to the next, and proceeds in each successive column until the bottom of the last column when both the X and Y away counters will have been decremented to a zero value. This coincidence causes the Y-home counter to be decremented by one count.
  • the X and Y away counters recycle to 0 to begin tracking the next interrogation cycle for a new "home" cell. Each time an X and Y home or away counter is decremented, the corresponding ALU 67 is incremented.
  • the Y-home counter when it completes its cycle from 15 to 0, decrements the X-home counter in the same manner as the Y-away counter stepped the X-away counter.
  • the preset values in the mask registers will prevent the output address from exceeding the value of an available address.
  • the counters merely provide the frequency division to effect the column stepping and cycle point counting.
  • each one of the 128 cells becomes a "home” cell.
  • Each "home” cell has a corresponding 128 "away” cells for a total 16,384 steps, but only 1024 repeat cycles of 16 counts each.
  • the X-away counter will have been decremented 1024 times, or experienced 128 repeat cycles.
  • Another example of memory address sequencing is the known diagonal mode. All diagonals are 45° diagonals and the number of cells in any one diagonal sequence is the same for any one memory.
  • the cells in a diagonal may be aligned, as in the major diagonal of a square, or they may be disposed in two parallel diagonal lines. Again, using the 8x16 memory for illustrative purposes, the number of diagonals will be equal to the greater of the two dimensions (16) and the number of cells in each respective diagonal will be equal to the lesser of the two dimensions (8). There will be nine continuous diagonals and seven discontinuous diagonals wherein the sum of the cells in the two discontinuous diagonals will be eight.
  • the X and Y address generators are set with zero offset and an increment constant for one.
  • the mask for the X addresses will be set to a binary value of seven and the Y mask will be set to a binary value of fifteen. Both address generators will be concurrently incremented by one count. This will provide successive addresses of cells along the 45° diagonal.
  • the X addresses will repeat the series 0-7 sixteen times even though the base address produced by the ALU 67A and buffer store 64A will advance from 0 through 127, the masking inhibiting usage of any address in excess of seven.
  • the Y-address generator will cycle concurrently with the X generator from zero upward by means of clock pulses applied to line 65C. However, to prevent a recycling of the Y addresses along the same diagonal it is necessary to add an additional count to the Y address after every sixteen counts so as to precess the diagonal one matrix position. This necessity is illustrated by the tabular succession of matrix positions shown in Fig. 3.
  • both counters achieve a simultaneous count of 0 at the end of each diagonal or eight times in the chosen example. This occurrence causes an additional count to be entered in the Y-ALU to precess the diagonal by one Y position.
  • the only remaining timing function is to detect the end of test. This can be accomplished in a variety of ways, either by counting the number of accesses, or by counting the number of diagonals. In the former, a counter preset to 127 and decremented would signal the end of test when it decremented to 0. The other would be to preset a counter to 7 and decrement it each time the X and Y counter had simultaneous zeroes. When this counter receives its final decrementing pulse at the last pair of zeros to recycle it to its preset value of 7, the cycle is finished.
  • the foregoing example may be extrapolated to larger memories by appropriate adjustment of the parameters, taking cognizance of the rules governing the number of cells in a diagonal and the number of diagonals. Also, a discrete small area of a larger memory may be tested by using the same addressing principles and sequences, and adding an offset to the X and Y addresses.
  • the preset data set into the address generator and the cycle counters can be adjusted to define the area of the memory to be tested and the patterns of the test.
  • the home and away feature need not be confined to individual cell sequences, but may also be used to test corresponding areas of a memory which share sense amplifiers.
  • the home and away addresses would then follow the same sequence, having identical incremental values, masking and cycle counting controls but differ only in their offsets. Alternate home and away addressing would test a succession of cells occupying the same relative positions with respect to two different geometric areas of the memory.
  • logic elements interconnected as hereinabove described provide for a very large variety of memory address sequences without requiring a large external memory to provide the sequences.
  • the external memory need only provide the output data to the address generator and the cycle counters.
  • the address generator then proceeds to produce the sequence of addresses without further reference to the external memory.
  • the "hard-wired" address generator provides faster testing by eliminating the constant need to interrogate the external memory for further instructions.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Claims (10)

1. Dispositif pour produire une suite sélectionnée parmi une pluralité de suites de valeurs numériques représentatives d'éléments d'une mémoire bidimensionnelle de stockage de données devant être testée, caractérisé par deux couples de moyens générateurs d'adresses, un couple pour chaque dimension,
chaque couple étant constitué par des premiers (A, B) et des seconds (C, D) moyens générateurs d'adresses, les premiers moyens générateurs d'adresses f'un couple étant associés à une cellule de mémoire de départ, qui est la cellule de référence pour une suite de cellules "distantes",
chacun desdits premiers et desdits seconds moyens générateurs d'adresses étant apte à agir en réponse à des valeurs numériques préétablies et à la réception d'impulsions de cadencement pour produire une suite de valeurs numériques représentatives des adresses respectives des éléments de mémoire devant être testés, et
des moyens de sélection (50, 60) raccordés aux sorties desdits moyens générateurs d'adresses de chacun desdits couples et étant aptes à agir en réponse à des impulsions de cadencement prédéterminées pour sélectionner les sorties desdits premiers ou seconds moyens générateurs d'adresses.
2. Dispositif selon la revendication 1, dans lequel chacun desdits premiers et desdits seconds moyens générateurs d'adresses (A, B) comprend
des moyens de comptage (63, 64, 67) aptes à agir en réponse à une succession d'impulsions de cadencement et à une valeur différentielle préétablie pour engendrer une succession de valeurs numériques, dont chacune diffère de la précédente dans la succession, de la valeur prédéterminée,
des moyens de commande (71) aptes à agir en réponse à une commande préétablie et raccordés à la sortie desdits moyens de comptage pour amener la valeur de la sortie desdits moyens de comptage à monter ou descendre,
des moyens de masquage (62, 72) raccordés à la sortie desdits moyens de commande et aptes à agir en réponse à une valeur prédéterminée pour empêcher la valeur de la suite numérique de dépasser une valeur inférieure de un à la valeur préétablie, et des moyens (61, 68) pour ajouter une valeur constante à chaque valeur de la suite de valeurs numériques de la suite de nombres après que la suite est inhibée par lesdits moyens de masquage,
de telle sorte que lesdits premiers moyens générateurs d'adresses (A, C) engendrent une première suite unique d'adresses de mémoire et que lesdits seconds moyens générateurs d'adresses (B, D) engendrent une seconde suite unique d'adresses de mémoire, et que lesdits moyens de sélection (58, 60) sélectionnent l'imbrication des première et seconde suites.
3. Dispositif selon la revendication 2, dans lequel lesdits moyens de comptage comprennent
un premier registre de stockage (63) mémorisant la différentielle préétablie, sous la forme de bits,
un second registre de stockage (64) apte à agir en réponse à une impulsion de cadencement de manière à recevoir et mémoriser un nombre binaire et à engendrer une sortie du nombre ainsi mémorisé,
un additionneur binaire (67), dont les entrées sont raccordées aux sorties desdits premier et second registres de stockage et dont la sortie est raccordée à l'entrée dudit second registre de stockage,
de telle sorte que ledit additionneur engendre une succession de nombres binaires dont chacun est supérieure, de façon incrémentale, au nombre précédent, d'une valeur égale à la différentielle préétablie dans ledit premier registre, en réponse aux impulsions de cadencement reçues par ledit second registre de stockage.
4. Dispositif selon la revendication 3, dans lequel lesdits moyens de commande comprennent une porte OU-Exclusif (71) à bits multiples, recevant comme première entrée la sortie à bits multiples dudit additionneur binaire (67) et comme seconde entrée rien que des zéros binaires ou rien que des uns binaires, ce qui amène la sortie de la porte OU-Exclusif à délivrer une suite ascendante ou descendante de nombres binaires.
5. Dispositif selon la revendication 4, dans lequel lesdits moyens de masquage comprennent une porte OU (72) à bits multiples, possédant un première entrée à bits multiples provenant de ladite porte OU-Exclusif et une seconde entrée provenant de la sortie d'un registre de stockage à bits multiples (62) mémorisant la valeur binaire de l'adresse la plus élevée, au-delà de laquelle l'adressage doit être inhibé, ladite valeur étant égale à 2"-', n étant un entier.
6. Dispositif selon la revendication 1, dans lequel lesdits moyens générateurs d'adresses (A, C) de chacun des couples produit une adresse de mémoire X et lesdits seconds moyens générateurs d'adresses (B, D) de chacun des couples produit une adresse de mémoire Y, de telle sorte qu'une sélection alternée des premiers générateurs d'adresses X et Y ou des seconds générateurs d'adresses X et Y produit une première et une seconde suites d'adresses de mémoire.
7. Dispositif selon l'une quelconque des revendications précédentes, caractérisé parson utilisation dans un dispositif servant à tester le fonctionnement d'une mémoire bidimensionnelle de stockage de données, adressable au moyen de premier et second générateurs d'adresses X (A, C) et de premier et second générateurs d'adresses Y (B, D) de telle sorte que les moyens de sélection (50, 60) peuvent agir en réponse à un signal de commande pour sélectionner les sorties soit desdits premiers générateurs d'adresses, soit desdits seconds générateurs d'adresses, et chacun desdits générateurs possède essentiellement les mêmes composants, mais en étant chacun apte à agir en réponse à des signaux d'horloge à caden- cements différents et à des données préétablies différentes pour fournir des suites respectives différentes de premières et de secondes adresses X et Y.
8. Dispositif selon la revendication 7, dans lequel chacun desdits générateurs d'adresses (A-D) comprend un premier additionneur à bits multiples (67) comportant deux entrées à bits multiples et une seule sortie à bits multiples qui est la somme des deux entrées,
un registre de stockage à bits multiples (63) mémorisant une constante et raccordé de manière à constituer une entrée dudit additionneur,
un autre registre de stockage à bits multiples (64) raccordé à la sortie dudit additionneur et apte à agir en réponse à une impulsion de cadencement pour mémoriser la sortie dudit additionneur, la sortie dudit autre registre étant raccordée en tant qu'entrée audit additionneur, de telle sorte que le contenu dudit additionneur est incrémenté d'une valeur égale à la constante mémorisée lors ds l'apparition de chaque impulsion de cadencement,
une porte OU-Exclusif à bits multiples (71) recevant comme première entrée la sortie dudit additionneur et comme seconde entrée rien que des zéros binaires ou rien que des uns binaires, de telle sorte que la sortie dudit additionneur est transmise par ladite porte OU-Exclusif sous la forme d'une suite ascendante de nombres binaires ou bien est convertie en une suite descendante de nombres binaires, respectivement,
une porte ET à bits multiples (72) recevant comme première entrée la sortie à bits multiples de ladite porte OU-Exclusif et une seconde entrée provenant d'un registre de stockage à bits multiples (62) mémorisant la valeur binaire 2"-' de l'adresse la plus élevée au-delà de laquelle, l'adressage doit être inhibé, n étant un entier,
un second additionneur (68) recevant sur l'une des entrées le contenu préétabli d'un registre de stockage à bits multiples (61) mémorisant le décalage de l'origine de la zone de mémoire devant être testée, par rapport à l'origine de référence des adresses de l'ensemble de la mémoire matricielle,
de telle sorte que chacun des premier et second généraleurs d'adresses X et Y engendre sa propre suite discrète et unique d'adresses en fonction des impulsions de cadencement qui y sont appliquées et des variables préétablies qui y sont introduites, et que les adresses sélectionnées pour le test de la mémoire sont commandées par les signaux de commande appliquées auxdits moyens de sélection.
9. Dispositif selon l'une des revendications 1 à 8, pour produire une suite sélectionnée parmi une pluralité de suites répétitives de nombres binaires pour fournir l'une des adresses de coordonnées pour tester une mémoire matricielle, caractérisé par un premier registre de stockage (63) mémorisant une première constante,
un second registre de stockage (64) apte à agir en réponse à une impulsion d'horloge pour recevoir et mémoriser des données,
un premier additionneur (67), dont les entrées sont raccordées aux sorties desdits premier et second registres et dont la sortie est raccordée à l'entrée dudit second registre, une porte OU-Exclusif (71) recevant comme première entrée rien que des zéros ou uns binaires et une seconde entrée en provenance dudit additionneur,
un troisième registre de stockage (62) mémorisant la valeur binaire de l'adresse la plus élevée au-delà de laquelle l'adressage soit être inhibé,
une porte ET (72) raccordée aux sorties de ladite porte OU-Exclusif et dudit troisième registre, un quatrième registre de stockage (61) mémorisant une seconde constante, et
un second additionneur (68) possédant une première entrée raccordée à la sortie de ladite porte ET et une seconde entrée raccordée audit quatrième registre.
10. Procédé pour produire des suites sélectionnées parmi une pluralité de suites répétitives de nombres binaires pour tester une mémoire matricielle à l'aide du dispositif selon la revendication 9, selon lequel une suite de nombres binaires ascendants, dont chacun est supérieur au précédent de la valeur d'une première constante mémorisée, est produite en réponse à une succession d'impulsions d'horloge reçues, ladite suite étant transmise sans être modifiée ou en étant convertie en une suite descendante, la suite ascendante ou descendante résultante étant empêchee et dépasser une valeur binaire inférieure de un à un nombre choisi mémorisé et étant amenée à répéter la suite lorsque la valeur d'inhibition est atteinte, et la valeur de la suite ainsi limitée est décalée en fonction d'une seconde constante mémorisée.
EP83100018A 1982-03-05 1983-01-04 Générateur de séquence d'adresses de mémoire Expired EP0088202B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/354,971 US4442519A (en) 1982-03-05 1982-03-05 Memory address sequence generator
US354971 1994-12-13

Publications (3)

Publication Number Publication Date
EP0088202A2 EP0088202A2 (fr) 1983-09-14
EP0088202A3 EP0088202A3 (en) 1987-06-03
EP0088202B1 true EP0088202B1 (fr) 1989-06-14

Family

ID=23395685

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83100018A Expired EP0088202B1 (fr) 1982-03-05 1983-01-04 Générateur de séquence d'adresses de mémoire

Country Status (4)

Country Link
US (1) US4442519A (fr)
EP (1) EP0088202B1 (fr)
JP (1) JPS58153300A (fr)
DE (1) DE3380080D1 (fr)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3237365A1 (de) * 1982-10-08 1984-04-12 Siemens AG, 1000 Berlin und 8000 München Anordnung zur erzeugung von mustern von pruefsignalen bei einem pruefgeraet
US4751631A (en) * 1983-02-04 1988-06-14 Signal Processing Systems, Inc. Apparatus for fast generation of signal sequences
US4715034A (en) * 1985-03-04 1987-12-22 John Fluke Mfg. Co., Inc. Method of and system for fast functional testing of random access memories
DE3513551A1 (de) * 1985-04-16 1986-10-16 Wandel & Goltermann Gmbh & Co, 7412 Eningen Digitaler wortgenerator zur automatischen erzeugung periodischer dauerzeichen aus n-bit-woertern aller wortgewichte und deren permutationen
JPS6224500A (ja) * 1985-07-23 1987-02-02 Yokogawa Electric Corp 半導体メモリ検査装置
CA1259680A (fr) * 1986-05-06 1989-09-19 Mosaid Technologies Inc. Brouilleur de signaux numeriques
JPS633240U (fr) * 1986-06-25 1988-01-11
US4852096A (en) * 1987-08-14 1989-07-25 International Business Machines Corp. CN2 test pattern generator
US5392302A (en) * 1991-03-13 1995-02-21 Quantum Corp. Address error detection technique for increasing the reliability of a storage subsystem
EP0573179A3 (en) * 1992-06-02 1996-06-05 American Telephone & Telegraph Non-fully-decoded test address generator
JPH08305638A (ja) * 1995-05-01 1996-11-22 Nec Corp Ｒｏｍデータ検査方法
US6061815A (en) * 1996-12-09 2000-05-09 Schlumberger Technologies, Inc. Programming utility register to generate addresses in algorithmic pattern generator
JP3235523B2 (ja) * 1997-08-06 2001-12-04 日本電気株式会社 半導体集積回路
US6073263A (en) * 1997-10-29 2000-06-06 Credence Systems Corporation Parallel processing pattern generation system for an integrated circuit tester
US6078637A (en) 1998-06-29 2000-06-20 Cypress Semiconductor Corp. Address counter test mode for memory device
US6934762B1 (en) 2000-04-27 2005-08-23 Redundant Networks, Inc. Method and apparatus for providing backup internet access

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3751649A (en) * 1971-05-17 1973-08-07 Marcrodata Co Memory system exerciser

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2829709C2 (de) * 1978-07-06 1984-02-23 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren und Anordnung zur Erzeugung zeitlich unmittelbar aufeinanderfolgender Impulszyklen
JPS5552581A (en) * 1978-10-11 1980-04-17 Advantest Corp Pattern generator
JPS6030973B2 (ja) * 1980-01-18 1985-07-19 日本電気株式会社 高速パタ−ン発生器
US4370746A (en) * 1980-12-24 1983-01-25 International Business Machines Corporation Memory address selector

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3751649A (en) * 1971-05-17 1973-08-07 Marcrodata Co Memory system exerciser

Also Published As

Publication number Publication date
JPS6231440B2 (fr) 1987-07-08
EP0088202A3 (en) 1987-06-03
JPS58153300A (ja) 1983-09-12
EP0088202A2 (fr) 1983-09-14
US4442519A (en) 1984-04-10
DE3380080D1 (en) 1989-07-20

Similar Documents

Publication Publication Date Title
EP0088202B1 (fr) Générateur de séquence d'adresses de mémoire
US4675546A (en) Edge programmable timing signal generator
US4639919A (en) Distributed pattern generator
US4270181A (en) Data processing system having a high speed pipeline processing architecture
US4739474A (en) Geometric-arithmetic parallel processor
US5325367A (en) Memory device containing a static ram memory that is adapted for executing a self-test, and integrated circuit containing such a device as an embedded static ram memory
DE60116046T2 (de) Eingebaute Selbsttestschaltung mit einem Schieberegister mit linearer Rückkopplung
DE69011133T2 (de) Verfahren und gerät zur hochgenauigen erzeugung von gewichteten zufallsmustern.
GB1589353A (en) Digital pattern triggering circuit
US4506341A (en) Interlaced programmable logic array having shared elements
US4586181A (en) Test pattern generating apparatus
US5485467A (en) Versatile reconfigurable matrix based built-in self-test processor for minimizing fault grading
US4068305A (en) Associative processors
KR840001731A (ko) 순차적인 워어드가 정열된 어드레스 지정장치
EP0574672A1 (fr) Générateur ajustable de configurations aléatoires pondérées de test pour des circuits logiques
US6513138B1 (en) Pattern generator for semiconductor test system
US5835428A (en) Method of testing semiconductor memory and apparatus for carrying out the method
CA1259680A (fr) Brouilleur de signaux numeriques
US5155826A (en) Memory paging method and apparatus
US3564514A (en) Programmable logic apparatus
US6108803A (en) Memory cell circuit for executing specific tests on memory cells that have been designated by address data
US4575815A (en) Data storage unit
JP2841456B2 (ja) データ転送方法及びデータバッファ装置
GB2141829A (en) Digital circuit testing arrangement
EP0199890A2 (fr) Circuit logique auto-séquencé

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE FR GB IT

17P Request for examination filed

Effective date: 19840126

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB IT

17Q First examination report despatched

Effective date: 19880120

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

REF Corresponds to:

Ref document number: 3380080

Country of ref document: DE

Date of ref document: 19890720

ET Fr: translation filed
ITF It: translation for a ep patent filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
ITTA It: last paid annual fee
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19921222

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19921223

Year of fee payment: 11

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19940104

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19940329

Year of fee payment: 12

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19940104

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19940930

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19951003