EP0065182B1 - Système d'identification électronique - Google Patents

Système d'identification électronique Download PDF

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Publication number
EP0065182B1
EP0065182B1 EP82103815A EP82103815A EP0065182B1 EP 0065182 B1 EP0065182 B1 EP 0065182B1 EP 82103815 A EP82103815 A EP 82103815A EP 82103815 A EP82103815 A EP 82103815A EP 0065182 B1 EP0065182 B1 EP 0065182B1
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EP
European Patent Office
Prior art keywords
key
lock
code
circuit
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP82103815A
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German (de)
English (en)
French (fr)
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EP0065182A3 (en
EP0065182A2 (fr
Inventor
Alain Marie-Louis Mole
Jean-Louis Paul Jules Savoyet
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Individual
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Individual
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Publication date
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Priority to AT82103815T priority Critical patent/ATE35468T1/de
Publication of EP0065182A2 publication Critical patent/EP0065182A2/fr
Publication of EP0065182A3 publication Critical patent/EP0065182A3/fr
Application granted granted Critical
Publication of EP0065182B1 publication Critical patent/EP0065182B1/fr
Expired legal-status Critical Current

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    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07C—TIME OR ATTENDANCE REGISTERS; REGISTERING OR INDICATING THE WORKING OF MACHINES; GENERATING RANDOM NUMBERS; VOTING OR LOTTERY APPARATUS; ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDED FOR ELSEWHERE
    • G07C9/00—Individual registration on entry or exit
    • G07C9/00174—Electronically operated locks; Circuits therefor; Nonmechanical keys therefor, e.g. passive or active electrical keys or other data carriers without mechanical keys

Definitions

  • the present invention relates to an identification system, for example of a person, for the control of an electrical, mechanical or other device.
  • Systems of identification or recognition of people of this type have many applications. They are used in particular for opening doors, managing schedules, managing devices used by several people such as photocopying machines or even in systems for distributing banknotes by credit cards.
  • a removable part which includes an identification code and which is in the form of a badge in the form of a credit card which the person to be identified carries with it (see by example U.S. Patent 3,637,994).
  • the identification code is materialized in the badge either by perforations or by a magnetic strip.
  • the use of such badges has many drawbacks. They are indeed relatively bulky and can deteriorate easily. In the case of punched badges, the code is relatively easy to recognize.
  • the carrier of the identification code is magnetic, the magnetic tape can be damaged by scratches or under the influence of magnets.
  • the device used for reading badges of this type is necessarily complex and must in particular include a mechanical drive system enabling the badge to be moved in order to read the identification code. As a result, the reading devices have a high production cost.
  • a removable part is used in the form of an electronic key similar to a conventional key but comprising means for memorizing an identification code which can be detected and recognized by a system.
  • reading device similar to a lock but comprising a set of electronic circuits (see for example American patent 4,038,637).
  • a programmable memory key system in which the identification code can be contained in a shift register housed in the electronic key.
  • the information contained in the key can be read by the electronic lock by means of pulses supplied by a clock located in said lock.
  • the information thus obtained is compared with a code stored in the lock so as to determine the identity of the two codes and the command, for example the opening of a strike or any other desired operation.
  • the present invention relates to an identification system which significantly improves the security of the identification systems currently used and known and in which the mobile part analogous to a key is inert so that the simple reading of the shift register contained in the key does not allow simple identification of the identification code.
  • the invention also relates to such a system in which the reading process involves one or more modifications of the content of this memory thus making any fraudulent duplication extremely difficult.
  • the electronic identification system comprises a mobile part similar to an electronic key intended to cooperate, by electrical coupling, with a fixed part similar to an electronic lock.
  • the fixed part comprises a clock modulation circuit for counting the aforementioned determined number of clock pulses emitted by a read circuit.
  • the clock modulation circuit is connected to a read stop circuit in order to further authorize the emission of an additional number of clock pulses or read pulses equal to the number of bits of the code. identification.
  • the mobile part can also include means for counting the determined number of successive clock pulses emitted by the fixed part and a logic gate so as to not allow the transfer of the contents of the memory of the mobile part to the memory of the fixed part. only after the emission of the aforementioned determined number of clock pulses causing the permutations which have just been indicated.
  • the fixed part which comprises a logic gate receiving the output signal from the memory of the mobile part as well as the output of the clock modulation circuit.
  • the means for generating a loading pulse included in the fixed part or electronic lock, comprise a loading circuit advantageously provided with a double flip-flop of the master-slave type associated with a NAND gate receiving clock pulses and providing a loading pulse.
  • the electronic means included in the fixed part for reading the content of the shift register of the mobile part preferably comprises a reading circuit advantageously provided with a double flip-flop of the master-slave type associated with a NAND gate receiving the pulses d 'aforementioned clock and connected to the output of the means providing the loading pulse.
  • the reading circuit is triggered after the emission of the loading pulse and supplies successive pulses allowing first of all a series of permutations of the content of the shift register of the mobile part then the serial reading of the information contained in said parallel / serial shift register.
  • a read stop circuit makes it possible to limit the number of read pulses to the exact number of bits contained in the shift register of the mobile part after the permutation phase.
  • This read stop circuit advantageously comprises a pulse counter receiving the read pulses from the read circuit when the additional number of pulses counted after the permutation phase corresponds to the number of bits in the shift register, this is ie when the content of the shift register of the mobile part has been read once.
  • the memory area of the mobile part preferably comprises a plurality of switches which can be produced for example in the form of fuses or by destroyable connections and whose position determines the electronic code identification.
  • Each flip-flop of the shift register of the mobile part is associated with one of the switches whose position controls its state by means of two NAND gates receiving the loading pulse on one of their inputs.
  • the first of the aforementioned NON AND gates is connected by its other input to the switch with which it is associated.
  • the second NAND gate receives the output of the first gate on its other input.
  • each flip-flop of the shift register is placed in a state corresponding to that of the switch with which it is associated.
  • the identification code initially represented by the position of the plurality of switches is transferred to the various flip-flops of the shift register under the action of the loading pulses.
  • the system can also comprise, in the fixed part, a circuit for authorizing successive tests.
  • This circuit comprises a succession of flip-flops, the resetting of which depends on the positive result of the comparison made by the comparison means with the code preprogrammed in the fixed part. In this way, a number of unsuccessful attempts is authorized equal to the number of flip-flops in this succession of flip-flops before triggering an alarm.
  • Suitable timing means can also be provided to reset all of the system's rockers to zero when the key is inserted and after uncoupling.
  • a so-called negative logic is used, that is to say for which we have adopted by convention level 1 for the ground potential and level 0 for the supply voltage which is preferably very low. of the order of + 5 volts.
  • level 1 for the ground potential
  • level 0 for the supply voltage which is preferably very low. of the order of + 5 volts.
  • the current demand remains limited to a few milliamps so as to avoid any danger for the user.
  • the identification system of the invention comprises a mobile or removable transportable part or electronic key shown in FIG. 2 and a fixed part or electronic lock shown in FIG. 1.
  • the removable part is presented like a classic key. It can advantageously consist of a glass fiber plate sandwiched by two thicknesses of hard plastic resistant well to solvents and to extreme temperatures.
  • the electronic key is therefore very resistant and its wear negligible in particular compared to that of a badge of the conventional type.
  • the electronic key comprises a certain number of electrical contacts constituted by conductive elements embedded in the plastic material cooperating on the side of the fixed part playing the role of electronic lock, with steel balls held by springs not illustrated in the figures. It is also possible to envisage making these contacts in another way, for example by optoelectronic link.
  • the electronic key shown diagrammatically includes a parallel / serial shift register referenced 9 as a whole, controlled by a succession of sixteen switches 10 connected to ground via the lock and whose open or closed position defines the set of bits of the identification code.
  • the switches 10 can for example be constituted by connections, part of which was initially destroyed so as to cut the electrical connection between the two terminals. Only the main terminals of the key have been shown in fig. 2.
  • the terminals 11 and 12 connected together in the key by a link not shown are intended to be connected to the system ground (T).
  • the terminal L referenced 13 is intended to receive a pulse for loading the code contained in the set of switches 10 into the register 9.
  • the terminal H referenced 14 is intended to receive a succession of pulses allowing the reading of the information contained in the shift register 9.
  • the terminals A referenced 15 and 16 connected together in the key by a link not shown are intended to be connected to the electric current supply located in the lock.
  • the output terminal S referenced 17 is connected to the output Q of the shift register 9.
  • the electronic key is passive and does not include a power source. As long as it is not coupled to the lock, the shift register 9 does not include any information and its reading therefore cannot provide the identification code.
  • the electronic lock illustrated in fig. 1 comprises a charging circuit referenced 18 as a whole, the input of which is connected to terminal 12 when the key is coupled with the lock, that is to say with the earth of the system and the output of which provides a pulse of loading on terminal L.
  • the output of the charging circuit 18 is also connected by connection 19 to the input of a reading circuit referenced 20 as a whole and supplying on terminal H a succession of pulses emitted by a clock circuit 21.
  • the output of the read circuit 20 is further connected by the connections 20a and 20b to the input of a clock modulation circuit 122 the output of which is connected by the connections 135 and 139 to the input of a circuit stop reading referenced 23 as a whole.
  • the output of the read stop circuit returns via the connection 24 to the read circuit 20 in order to deliver a read stop pulse stopping the emission of the clock pulses on the terminal H when the content of the shift register 9 was read once, i.e. when a total number of sixteen read pulses appeared on terminal H.
  • the terminal S connected to the output Q of the shift register 9 receives the serial signal representing the information contained in the shift register 9.
  • the terminal S is connected to the input E of a circuit 25 performing a serial / parallel conversion and a comparison of the information read from the key with an identification code preprogrammed in the electronic lock itself and constituted in the example illustrated in the form of a set of switches 26 preprogrammed.
  • the electronic lock further comprises in the example illustrated a circuit for authorizing successive tests 27 connected by an output connection 28 to an alarm device which is actuated after four successive unsuccessful tests.
  • a circuit 29 connected to the terminals A of the key makes it possible to stabilize the supply at + 5 volts.
  • a first reset circuit 30 causes all of the flip-flops and counters of the electronic key system to be reset to zero when the key is coupled to the lock.
  • a second reset circuit 31 causes all of the flip-flops and counters to be reset to zero and the supply cut off when the key is uncoupled.
  • a door release control circuit 32 receives a signal when the comparison made in circuit 25 is positive.
  • the loading circuit 18 comprises a double master-slave flip-flop constituted by a first flip-flop 33 or "master” and a second flip-flop 34 "slave".
  • the two flip-flops 33, 34 are connected to each other in a conventional manner, the second flip-flop 34 receiving on its input t the clock signal coming from the clock circuit 21.
  • the output Q of flip-flop 34 is connected to one of the NAND gate 35 inputs further receiving on its second input the clock signal.
  • the input t of the first flip-flop 33 is connected via the two timers 36 and 37 to the ground of the system via terminal 12 connected to terminal T when the key is coupled to the lock. Under these conditions, the system therefore works well in negative logic.
  • the read circuit 20 is of the same type as the loading circuit 18 and it includes, like the latter, a double master-slave flip-flop 38, 39 mounted in the same way.
  • the input t of the first flip-flop 38 receives the loading pulse via the connection 19.
  • the NAND gate 41 connected to the output of the second flip-flop 39 in the same way as the NAND gate 35 of the charging circuit 18 therefore provides a succession of pulses on terminal H, these pulses being said in the following description, clock pulses or read pulses.
  • the output of the NI gate 137a is connected by the connection 139 to the read stop circuit 23 which includes a counter 42 whose outputs Q A , Q B , Qc and QD are connected to the input of a gate NON- AND 42a.
  • the outlet of door 42a is connected to the inlet ⁇ of a monostable 43.
  • the output pulses of the NON-ET41 gate or clock pulses appearing on the terminal H transmitted by the NI gate 137a to the input H of the counter 42 are counted until reaching the number of sixteen, corresponding in the example illustrated, the number of bits in the shift register 9 of the key, that is to say the number of switches 10.
  • the output ⁇ of the monostable 43 delivers an output signal applied by the connection 24 to the forcing input R of the first flip-flop 38 of the read circuit 20 resetting the latter to zero and thereby stopping the read pulses emitted by the circuit 20.
  • the serial signal appearing on terminal S and representing the content of register 9 feeds the input E of a serial / parallel converter comprising two serial / parallel shift registers 45a and 45b included in the conversion and comparison circuit 25.
  • the clock pulses or read pulses are also applied by the connections 46a and 46b as well as the inverter 46d connected to the exit from the NI 137a gate, at the H inputs of the two registers 45a and 45b.
  • the comparison code preprogrammed in the fixed part or electronic lock, materialized by the position of the switches 26, is compared with the result of the series / parallel conversion in the comparison circuit comprising the four comparators 47a, 47b, 47c, and 47d connected in series and connected on the one hand to the different parallel outputs of the two conversion registers 45a and 45b and on the other hand to the different switches 26 grouped by four for each of the comparators 47a to 47d.
  • the result of the comparison from the last element 47d is a "zero" or “one” signal depending on whether the comparison is negative or positive.
  • the result of this comparison appearing on the connection 51 is applied to the input D of the flip-flop 52 receiving further on its input T by the connections 63 and 53 the output signal of the read stop circuit 23.
  • a signal is emitted by the output Q of the flip-flop 52 and transmitted by the connection 54 via the amplifier 55 to the relay 56 closing the switch 57 of the door release control circuit 32.
  • the signal emitted by the output to of the flip-flop 52 is transmitted by the connection 58 to the NAND gate 59 whose output is connected by the inverter 59a to the reset reset forcing inputs R of the three flip-flops 60, 61 and 62 of the successive test authorization circuit 27 connected in cascade and connected to the alarm control 28.
  • the input T of the first flip-flop 60 receives the output signal from the read stop circuit 23 through connection 63.
  • the power supply stabilization circuit 29 comprises an input terminal 64 connected to the supply battery, for example + 5 volts, contained in the electronic lock but not shown in the figure.
  • the two terminals 15 and 16 intended to cooperate with the corresponding terminals of the key are mounted via the capacitor 65 and the diode 66.
  • the electronic lock further comprises, in the first reset circuit 30, a monostable 70 receiving on its input ⁇ by connection 71 the output signal of the timer 36. Under these conditions, the monostable 70 reacts to a signal having a falling edge on connection 71, that is to say when the key is coupled.
  • the output Q of the monostable 70 is connected by the link 72 to one of the inputs of the NAND gate 73.
  • the output signal of the NAND gate 73 allows via the inverter 74 and by the connections 75, 76a and 76b to reset to zero by their forcing inputs A the two registers 45a and 45b of the series / parallel conversion circuit 25.
  • the output Q of the monostable 70 is also connected by connection 78 to one of the inputs of the NAND gate 79 receiving on its other input the output signal of the read stop circuit 23.
  • the output of the NAND gate 79 resets the counter 42 by connection 79a.
  • the circuit 31 for resetting to zero at the end of reading when the key is removed comprises two monostables 80 and 81 connected in cascade, the output Q of the monostable 80 being connected to the input A of the monostable 81.
  • the first monostable 80 receives on its input B via connection 82 the output signal of timer 37 and reacts, taking into account this arrangement, on a signal having a rising edge on connection 82, that is to say during uncoupling of the key.
  • the output ⁇ of the second monostable 81 which provides a very short pulse is connected by the connection 83 to the second input of the NAND gate 73 which causes, as we have seen previously, the resetting of the conversion circuit series / parallel 25.
  • the Q output of monostable 81 is also connected by connection 84 to one of the inputs of NAND gate 59 so as to reset flip-flops 60, 61 and 62 of the test authorization circuit successive 27 when the key is uncoupled.
  • the rising edge signal on the connection 82 at the output of the timer 37 applied via the inverter 85 to the input T of the flip-flop 86 causes, via the amplifier 87 connected to its output Q, triggering of the relay 68 of the supply circuit 29 so that the supply is cut off.
  • the flip-flop 86 is reset to zero by its input A via the connection 84a connected to the output Q of the monostable 81 when the key is uncoupled from the lock.
  • the NAND gate 88 receives on its two inputs respectively the output signal from the NAND gate 73 via the inverter 74 and the connection 75 and the output signal from the inverter 85 via the connection 89.
  • the output signal from the NAND gate 88 allows the flip-flop 52 to be reset to zero by its input A by means of the connection 90 and the inverter 91 at the time of uncoupling of the key after the expiration of the timer delay time 37.
  • FIG. 3 The detailed structure of the shift register 9 of the key and of the set of switches 10 playing the role of preprogrammed memory is partially illustrated in FIG. 3.
  • the switch 10a is shown open which, in the negative logic chosen by way of example for the circuit of FIG. 2, corresponds to a "one" signal.
  • the switch 10b connected to ground is shown closed, which corresponds to a "zero" signal.
  • the other switches have not been shown in FIG. 3.
  • This figure also shows the first two flip-flops 92a and 92b corresponding to the first two bits of the register with offset 9 and which receive on their inputs H the clock signals or reading pulses coming from the reading circuit 20 of the lock by the connection 117 also illustrated in FIG. 2.
  • the different flip-flops 92a, 92b, etc ... are connected to each other in a cascade in a conventional manner, the outputs Q and to of each upstream flip-flop being connected to the inputs S and R of the immediately next flip-flop so as to produce the register shift 9.
  • Two NAND gates 95a and 96a are associated with the flip-flop 92a, the outputs of the two NAND gates being connected respectively to the input P placing the flip-flop 92a in the "one" state and to the input R placing the flip-flop 92a in the "zero" state.
  • the first NAND gate 95a is connected by its first input via the connection 97a to the switch 10a and by its second input via the connection 98a at the output of the inverter 99 receiving the charging pulse via terminal L via connection 112a also visible in fig. 2.
  • the output of the inverter 99 is also connected by the connection 100a to one of the inputs of the NAND gate 96a which receives on its other input by the connection 101a the output of the NAND gate 95a.
  • the forcing inputs S and R of the first flip-flop 92a are also connected via the inverters 102 and 103 to the connection 113 also visible in FIG. 2.
  • the clock modulation circuit 122 comprises a set of three counters 124, 125 and 126.
  • the first counter 124 receives on its input H the clock pulses or read pulses emitted by the read circuit 20
  • switches 124a which can be pre-programmed define by their positions a determined number and are connected to the outputs Q A , Q B , Q c and Q D of the counter 124.
  • the second counter 125 receives on its input H the output Q D of the first counter 124. It is also associated with four switches 125a whose position also defines a determined number and which are connected to the outputs Q A , Q B , Q c and Q D of counter 125.
  • a NAND gate 127 receives on its different inputs all the connections from the eight switches 124a and 125a.
  • the output of the gate 127 is connected by the connection 128 to the input H of the third counter 126 which is also associated with four switches 126a as is the case for the two counters 124 and 125.
  • the connections of the four switches 126a are connected to the inputs of a NAND gate 129.
  • the output of the gate 129 emits a signal after the emission of a number of clock pulses by the circuit 20 which depends on the position of the different switches 124a, 125a and 126a .
  • the number defined by the first two counters 124 and 125 corresponds to the number of read pulses within a cycle.
  • the number defined by the counter 126 corresponds to the number of cycles.
  • the total number defined by the entire modulation circuit 122 is the product of these two numbers. Of course, other means could be used for this counting.
  • the output signal of the NAND gate 129 appears at one of the inputs of the NI gate 137a by the connection 135.
  • the NI gate 137a receives on its second input via connection 138 the clock pulses emitted by the read circuit 20.
  • the number of clock pulses emitted is not equal to the number determined by the three groups of switches 124a, 125a and 126a, the NI 137a door remains blocked and does not emit any output signal.
  • the shift register 9 is looped back on itself, its output 0. being connected to its input E by the connection 113.
  • the NI 137a door opens. New read pulses always emitted by the read circuit 20 passing through the NI gate 137a are then transmitted by the connection 139 to the input of the read stop circuit 23 where they are counted.
  • the key further comprises a circuit 149 for controlling the number of clock pulses, analogous to the clock modulation circuit 122 of the lock.
  • the control circuit 149 comprises three counters 150, 151 and 152.
  • the first two counters 150 and 151 each associated with four programming switches 150a and 151a, supply a NAND gate 153 which is connected to its output by the connection 154 to the input of the third counter 152.
  • the latter is associated with four programming switches 152a connected to the four inputs of an AND gate 155.
  • the output of the AND gate 155 is connected by connection 156 to one of the inputs of a door AND 157, the second input of which is connected by connection 158 to the output Q of the shift register 9.
  • the output of the gate AND 157 is connected to the output terminal S.
  • the clock pulses or read pulses appearing on the terminal H are transmitted to the input H of the first counter 150 via connection 149a.
  • the three counters 150, 151 and 152 are reset to zero by means of a Schmidt flip-flop 119 connected to the supply by the resistor 120 and to the ground by the capacitor 121 and connected to the inputs R 2 of the three counters 150 , 151 and 152 through connection 149b. The reset is therefore carried out when the key is uncoupled.
  • the identification system illustrated in the figures operates as follows.
  • the entire system is switched on, the two terminals 15 and 16 being short-circuited.
  • the clock circuit 21 located in the lock emits successive pulses.
  • a falling edge signal causes, by the monostable 70, a reset pulse of the various elements of the lock.
  • the output of the second timer 37 delivers a falling edge signal which causes, after a second delay, the emission by the charging circuit of a negative charging pulse.
  • This pulse causes the connection 19a to reset the master flip-flop 33 of the loading circuit 18.
  • the appearance on terminal L of this single loading pulse transmitted by the connection 112a causes all the flip-flops to be loaded.
  • the charging pulse also transmitted by the connection 19 to the reading circuit 20 causes the start of the emission of clock pulses or reading pulses by the reading circuit 20.
  • These pulses transmitted by the connections 20a and 20b to the clock modulation circuit 122 are successively counted by the latter.
  • the same clock pulses appearing on the terminal H are transmitted by the connection 117 to the various clock inputs H of the flip-flops 92 of the shift register 9 each time causing a shift of a bit or a permutation of the content of register 9 due to loopback connection 113.
  • connection 149a the same clock pulses applied by the connection 149a to the input of the control circuit 149 are also counted by this latter circuit.
  • programming of the control circuit 149 by means of the three groups of switches 150a, 151 a and 152a is the same as that of the clock modulation circuit 122 of the lock depending on the position of the three groups of switches 124a, 125a and 126a.
  • the two counters 150 and 151 of the control circuit 149 play the same role as the two counters 124 and 125 of the clock modulation circuit 122 and count the number of clock pulses in a cycle.
  • the third counter 152 of the control circuit 149 plays the same role as the third counter 126 of the clock modulation circuit 122 and counts the number of cycles.
  • the AND gate 157 remains blocked so that the information contained in the shift register 9 is not transmitted to the terminal S and to the comparison circuit 25 of the lock.
  • the number of clock pulses counted by the clock modulation circuit 122 and verified by the control circuit 149 must not be a multiple of the number of bits of the shift register 9. In the otherwise, it is understood that the permutation would not entail any modification in the content of the shift register 9.
  • the number of pulses determined by the first two counters 124 and 125 of the circuit 122 and verified by the first two counters 150 and 151 of the control circuit 149 is greater than the number of bits of the shift register 9. De in this way, the reading pulses appearing on the terminal H after the various permutations effectively allow the reading of the entire content of the shift register 9 without the gate 157 being blocked by an absence of signal on the AND gate 155.
  • control circuit 149 has been provided in the key, it will be understood that it would be possible to remove, in a simplified variant, this control circuit on the condition of providing a logic gate to prevent the transfer of the serial signal representing the content of the shift register 9 before the end of the permutation phase.
  • a logic gate could for example be constituted by an AND gate disposed in the electronic lock connected by one of its inputs to the output terminal S and receiving on its other input the output of the clock modulation circuit 122 c ' that is to say in this case the output of the NAND gate 129.
  • the input of the comparison circuit 25 would then be connected to the output of this AND blocking gate.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Lock And Its Accessories (AREA)
  • Cash Registers Or Receiving Machines (AREA)
  • Testing Of Coins (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
  • Burglar Alarm Systems (AREA)
EP82103815A 1981-05-12 1982-05-04 Système d'identification électronique Expired EP0065182B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT82103815T ATE35468T1 (de) 1981-05-12 1982-05-04 Verfahren zur elektronischen identifikation.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8109452 1981-05-12
FR8109452A FR2506047B1 (fr) 1981-05-12 1981-05-12 Systeme d'identification electronique

Publications (3)

Publication Number Publication Date
EP0065182A2 EP0065182A2 (fr) 1982-11-24
EP0065182A3 EP0065182A3 (en) 1983-04-06
EP0065182B1 true EP0065182B1 (fr) 1988-06-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP82103815A Expired EP0065182B1 (fr) 1981-05-12 1982-05-04 Système d'identification électronique

Country Status (8)

Country Link
US (1) US4486751A (enrdf_load_stackoverflow)
EP (1) EP0065182B1 (enrdf_load_stackoverflow)
JP (1) JPS5820881A (enrdf_load_stackoverflow)
AT (1) ATE35468T1 (enrdf_load_stackoverflow)
CA (1) CA1187991A (enrdf_load_stackoverflow)
DE (1) DE3278725D1 (enrdf_load_stackoverflow)
ES (1) ES8304344A1 (enrdf_load_stackoverflow)
FR (1) FR2506047B1 (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6442986B1 (en) 1998-04-07 2002-09-03 Best Lock Corporation Electronic token and lock core

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES8502795A1 (es) * 1983-05-11 1985-01-16 Savoyet Jean L Dispositivo de identificacion electronica
US4686912A (en) * 1985-04-15 1987-08-18 The Protech Partnership Electrically controlled locking apparatus and safe utilizing same
JPH068162B2 (ja) * 1986-03-20 1994-02-02 三菱重工業株式会社 水素ガスの吸収方法
US4829296A (en) * 1986-04-30 1989-05-09 Carey S. Clark Electronic lock system
US5148534A (en) * 1986-11-05 1992-09-15 International Business Machines Corp. Hardware cartridge representing verifiable, use-once authorization
JPS63124154A (ja) * 1986-11-05 1988-05-27 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 暗証情報発生装置
CA1308565C (en) * 1987-01-20 1992-10-13 Ford Motor Company Of Canada, Limited Programmable key and improved lock assembly
GB9215683D0 (en) * 1992-07-23 1992-09-09 Ab Electronic Components Ltd A motor vehicle security system
JPH06234502A (ja) * 1993-02-10 1994-08-23 Mitsui Eng & Shipbuild Co Ltd 水素吸蔵合金スラリを用いたエネルギ貯蔵方法
JPH06234501A (ja) * 1993-02-10 1994-08-23 Mitsui Eng & Shipbuild Co Ltd 水素供給方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2136269A5 (enrdf_load_stackoverflow) * 1971-04-09 1972-12-22 Eastern Co

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3859634A (en) * 1971-04-09 1975-01-07 Little Inc A Digital lock system having electronic key card
SE381940B (sv) * 1972-04-11 1975-12-22 Gretag Ag Anordning for enskild identifiering av ett flertal individer
US3906460A (en) * 1973-01-11 1975-09-16 Halpern John Wolfgang Proximity data transfer system with tamper proof portable data token
US3872435A (en) * 1973-05-18 1975-03-18 Victor L Cestaro Opto-electronic security system
US3944976A (en) * 1974-08-09 1976-03-16 Rode France Electronic security apparatus
US4004133A (en) * 1974-12-30 1977-01-18 Rca Corporation Credit card containing electronic circuit
JPS5231632A (en) * 1975-08-14 1977-03-10 Matsushita Electric Ind Co Ltd Selling amount memory unit
US4031434A (en) * 1975-12-29 1977-06-21 The Eastern Company Keyhole-less electronic lock
FR2394131A1 (fr) * 1977-06-07 1979-01-05 Cii Honeywell Bull Systeme de traitement d'informations protegeant le secret d'informations confidentielles
FR2480010A1 (fr) * 1980-04-03 1981-10-09 Mole Alain Systeme d'identification, par exemple d'une personne, en vue de la commande d'un appareil electrique, d'un appareil mecanique ou de tout autre appareil

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2136269A5 (enrdf_load_stackoverflow) * 1971-04-09 1972-12-22 Eastern Co

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6442986B1 (en) 1998-04-07 2002-09-03 Best Lock Corporation Electronic token and lock core
US6668606B1 (en) 1998-04-07 2003-12-30 Best Access Systems Electronic token lock core

Also Published As

Publication number Publication date
EP0065182A3 (en) 1983-04-06
ES512058A0 (es) 1983-02-16
ATE35468T1 (de) 1988-07-15
FR2506047B1 (fr) 1986-02-07
DE3278725D1 (en) 1988-08-04
US4486751A (en) 1984-12-04
JPS5820881A (ja) 1983-02-07
JPH0418356B2 (enrdf_load_stackoverflow) 1992-03-27
CA1187991A (fr) 1985-05-28
EP0065182A2 (fr) 1982-11-24
FR2506047A1 (fr) 1982-11-19
ES8304344A1 (es) 1983-02-16

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