DE69936865D1 - Verfahren und apparat zur steuerung der datenrate einer taktgetriebeschaltung - Google Patents

Verfahren und apparat zur steuerung der datenrate einer taktgetriebeschaltung

Info

Publication number
DE69936865D1
DE69936865D1 DE69936865T DE69936865T DE69936865D1 DE 69936865 D1 DE69936865 D1 DE 69936865D1 DE 69936865 T DE69936865 T DE 69936865T DE 69936865 T DE69936865 T DE 69936865T DE 69936865 D1 DE69936865 D1 DE 69936865D1
Authority
DE
Germany
Prior art keywords
gearbox
clock
controlling
data rate
rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69936865T
Other languages
English (en)
Other versions
DE69936865T2 (de
Inventor
Troy A Manning
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of DE69936865D1 publication Critical patent/DE69936865D1/de
Publication of DE69936865T2 publication Critical patent/DE69936865T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Logic Circuits (AREA)
DE69936865T 1998-06-23 1999-06-23 Verfahren und apparat zur steuerung der datenrate einer taktgetriebeschaltung Expired - Lifetime DE69936865T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US103628 1993-08-06
US09/103,628 US6094727A (en) 1998-06-23 1998-06-23 Method and apparatus for controlling the data rate of a clocking circuit
PCT/US1999/014228 WO1999067789A1 (en) 1998-06-23 1999-06-23 Method and apparatus for controlling the data rate of a clocking circuit

Publications (2)

Publication Number Publication Date
DE69936865D1 true DE69936865D1 (de) 2007-09-27
DE69936865T2 DE69936865T2 (de) 2008-05-15

Family

ID=22296178

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69936865T Expired - Lifetime DE69936865T2 (de) 1998-06-23 1999-06-23 Verfahren und apparat zur steuerung der datenrate einer taktgetriebeschaltung

Country Status (8)

Country Link
US (2) US6094727A (de)
EP (1) EP1097455B1 (de)
JP (1) JP4392545B2 (de)
KR (1) KR100622841B1 (de)
AU (1) AU4711299A (de)
DE (1) DE69936865T2 (de)
TW (1) TW442717B (de)
WO (1) WO1999067789A1 (de)

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US6111446A (en) 1998-03-20 2000-08-29 Micron Technology, Inc. Integrated circuit data latch driver circuit
US6094727A (en) 1998-06-23 2000-07-25 Micron Technology, Inc. Method and apparatus for controlling the data rate of a clocking circuit
US6275546B1 (en) * 1998-06-30 2001-08-14 Hewlett-Packard Company Glitchless clock switch circuit
JP3948141B2 (ja) * 1998-09-24 2007-07-25 富士通株式会社 半導体記憶装置及びその制御方法
US6643787B1 (en) * 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
US6646953B1 (en) 2000-07-06 2003-11-11 Rambus Inc. Single-clock, strobeless signaling system
JP2002007200A (ja) * 2000-06-16 2002-01-11 Nec Corp メモリ制御装置及び動作切替方法並びにインターフェース装置、半導体集積チップ、記録媒体
US6492852B2 (en) 2001-03-30 2002-12-10 International Business Machines Corporation Pre-divider architecture for low power in a digital delay locked loop
US6392946B1 (en) * 2001-05-15 2002-05-21 Leadtek Research Inc. SDR and QDR converter and interface card, motherboard and memory module interface using the same
US6779075B2 (en) * 2001-05-15 2004-08-17 Leadtek Research Inc. DDR and QDR converter and interface card, motherboard and memory module interface using the same
US7190754B1 (en) 2001-12-24 2007-03-13 Rambus Inc. Transceiver with selectable data rate
US6928027B2 (en) * 2003-04-11 2005-08-09 Qualcomm Inc Virtual dual-port synchronous RAM architecture
US7243254B1 (en) * 2003-11-05 2007-07-10 Lsi Corporation Low power memory controller that is adaptable to either double data rate DRAM or single data rate synchronous DRAM circuits
US7299329B2 (en) 2004-01-29 2007-11-20 Micron Technology, Inc. Dual edge command in DRAM
EP1830363A4 (de) * 2004-12-24 2008-10-08 Spansion Llc Speicherbaustein des synchronisationstyps und steuerverfahren dafür
DE102005043487A1 (de) * 2005-09-13 2007-03-15 Abb Patent Gmbh Automatisierungstechnische Einrichtung
US7564737B2 (en) * 2006-08-30 2009-07-21 Advanced Micro Devices, Inc. Memory data transfer
US7882384B2 (en) * 2006-08-31 2011-02-01 National Semiconductor Corporation Setting and minimizing a derived clock frequency based on an input time interval
US9336342B2 (en) 2011-09-23 2016-05-10 Synopsys, Inc. Memory hard macro partition optimization for testing embedded memories
DE102012209712A1 (de) * 2012-06-11 2013-12-12 Robert Bosch Gmbh Aktive Funktionseinschränkung eines Mikrocontrollers
KR102000470B1 (ko) 2012-10-30 2019-07-16 삼성전자주식회사 듀티 정정 회로 및 이를 포함하는 시스템
US8972685B2 (en) 2012-12-21 2015-03-03 Intel Corporation Method, apparatus and system for exchanging communications via a command/address bus
JP2019145186A (ja) * 2018-02-21 2019-08-29 東芝メモリ株式会社 半導体記憶装置

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US4297641A (en) 1979-09-28 1981-10-27 Rca Corporation Serrodyning system employing an adjustable phase shifting circuit
US4527075A (en) * 1983-07-11 1985-07-02 Sperry Corporation Clock source with automatic duty cycle correction
US4956566A (en) 1988-01-28 1990-09-11 Siemens Aktiengesellschaft Circuit configuration with a generator system for path- or angle-dependent signals
US5165046A (en) * 1989-11-06 1992-11-17 Micron Technology, Inc. High speed CMOS driver circuit
US5128563A (en) * 1990-11-28 1992-07-07 Micron Technology, Inc. CMOS bootstrapped output driver method and circuit
US5128560A (en) * 1991-03-22 1992-07-07 Micron Technology, Inc. Boosted supply output driver circuit for driving an all N-channel output stage
JPH05204634A (ja) * 1991-08-29 1993-08-13 Internatl Business Mach Corp <Ibm> マイクロプロセツサ回路
US5274276A (en) * 1992-06-26 1993-12-28 Micron Technology, Inc. Output driver circuit comprising a programmable circuit for determining the potential at the output node and the method of implementing the circuit
US5347179A (en) * 1993-04-15 1994-09-13 Micron Semiconductor, Inc. Inverting output driver circuit for reducing electron injection into the substrate
US5371772A (en) * 1993-09-14 1994-12-06 Intel Corporation Programmable divider exhibiting a 50/50 duty cycle
DE4420377C2 (de) 1993-09-22 1998-08-27 Hewlett Packard Co Verfahren zum Erzeugen von Quadratursignalen
US5706407A (en) * 1993-12-28 1998-01-06 Kabushiki Kaisha Toshiba System for reallocation of memory banks in memory sized order
KR100393317B1 (ko) * 1994-02-15 2003-10-23 람버스 인코포레이티드 지연동기루프
US5589782A (en) * 1995-06-02 1996-12-31 Advanced Micro Devices, Inc. Macrocell and clock signal allocation circuit for a programmable logic device (PLD) enabling PLD resources to provide multiple functions
US5627487A (en) * 1995-06-28 1997-05-06 Micron Technology, Inc. Charge conserving driver circuit for capacitive loads
KR0159074B1 (ko) * 1995-12-23 1999-02-18 김광호 동기형 디램 장치의 데이터 출력 버퍼용 클럭 발생 회로
US5758134A (en) * 1996-09-04 1998-05-26 Radisys Corporation Microprocessor embedded control system having an automatic clock slowdown circuit
US5877636A (en) * 1996-10-18 1999-03-02 Samsung Electronics Co., Ltd. Synchronous multiplexer for clock signals
US5917758A (en) 1996-11-04 1999-06-29 Micron Technology, Inc. Adjustable output driver circuit
US5949254A (en) 1996-11-26 1999-09-07 Micron Technology, Inc. Adjustable output driver circuit
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
KR100238242B1 (ko) * 1997-04-22 2000-01-15 윤종용 반도체 메모리장치의 동작 제어장치
JPH10334659A (ja) * 1997-05-29 1998-12-18 Mitsubishi Electric Corp 同期型半導体記憶装置
US6072348A (en) * 1997-07-09 2000-06-06 Xilinx, Inc. Programmable power reduction in a clock-distribution circuit
US5874845A (en) * 1997-07-21 1999-02-23 International Business Machines Corporation Non-overlapping clock phase splitter
US5867453A (en) * 1998-02-06 1999-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Self-setup non-overlap clock generator
US6094727A (en) 1998-06-23 2000-07-25 Micron Technology, Inc. Method and apparatus for controlling the data rate of a clocking circuit

Also Published As

Publication number Publication date
US6415390B1 (en) 2002-07-02
DE69936865T2 (de) 2008-05-15
US6094727A (en) 2000-07-25
KR20010071575A (ko) 2001-07-28
EP1097455A1 (de) 2001-05-09
EP1097455B1 (de) 2007-08-15
KR100622841B1 (ko) 2006-09-12
JP2002519773A (ja) 2002-07-02
AU4711299A (en) 2000-01-10
JP4392545B2 (ja) 2010-01-06
TW442717B (en) 2001-06-23
WO1999067789A1 (en) 1999-12-29

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