DE69924179D1 - Breitbandige Speicheranordnung mit Befehlsstapel und schmaler Ein- und Ausgabe - Google Patents

Breitbandige Speicheranordnung mit Befehlsstapel und schmaler Ein- und Ausgabe

Info

Publication number
DE69924179D1
DE69924179D1 DE69924179T DE69924179T DE69924179D1 DE 69924179 D1 DE69924179 D1 DE 69924179D1 DE 69924179 T DE69924179 T DE 69924179T DE 69924179 T DE69924179 T DE 69924179T DE 69924179 D1 DE69924179 D1 DE 69924179D1
Authority
DE
Germany
Prior art keywords
output
memory arrangement
instruction stack
narrow input
broadband memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69924179T
Other languages
English (en)
Other versions
DE69924179T2 (de
Inventor
Timothy J Dell
Erik L Hedberg
Mark W Kellogg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69924179D1 publication Critical patent/DE69924179D1/de
Publication of DE69924179T2 publication Critical patent/DE69924179T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
DE69924179T 1998-05-15 1999-04-29 Breitbandige Speicheranordnung mit Befehlsstapel und schmaler Ein- und Ausgabe Expired - Lifetime DE69924179T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/079,572 US6065093A (en) 1998-05-15 1998-05-15 High bandwidth narrow I/O memory device with command stacking
US79572 1998-05-15

Publications (2)

Publication Number Publication Date
DE69924179D1 true DE69924179D1 (de) 2005-04-21
DE69924179T2 DE69924179T2 (de) 2006-03-23

Family

ID=22151394

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69924179T Expired - Lifetime DE69924179T2 (de) 1998-05-15 1999-04-29 Breitbandige Speicheranordnung mit Befehlsstapel und schmaler Ein- und Ausgabe

Country Status (5)

Country Link
US (1) US6065093A (de)
EP (1) EP0957490B1 (de)
JP (1) JP3384770B2 (de)
KR (1) KR100332188B1 (de)
DE (1) DE69924179T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62199687A (ja) * 1986-04-28 1987-09-03 ユニオン・オイル・コンパニ−・オブ・カリフオルニア 細孔の大きい触媒を用いる水素化法
US6334202B1 (en) * 1998-07-22 2001-12-25 Telefonaktiebolaget Lm Ericsson (Publ) Fast metric calculation for Viterbi decoder implementation
US6633944B1 (en) * 2001-10-31 2003-10-14 Lsi Logic Corporation AHB segmentation bridge between busses having different native data widths
US7554858B2 (en) * 2007-08-10 2009-06-30 Micron Technology, Inc. System and method for reducing pin-count of memory devices, and memory device testers for same
US8438356B2 (en) * 2007-10-01 2013-05-07 Marvell World Trade Ltd. Flash memory controller
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법
US20190074222A1 (en) * 2011-06-28 2019-03-07 Monolithic 3D Inc. 3d semiconductor device and system
KR102648180B1 (ko) 2016-07-19 2024-03-18 에스케이하이닉스 주식회사 메모리 시스템 및 그 동작 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228500A (en) * 1978-03-27 1980-10-14 Honeywell Information Systems Inc. Command stacking apparatus for use in a memory controller
US4635254A (en) * 1984-12-13 1987-01-06 United Technologies Corporation Coherent interface with wraparound receive memory
EP0340901A3 (de) * 1988-03-23 1992-12-30 Du Pont Pixel Systems Limited Zugriffsystem für Speicher mit doppelter Anschlussstelle
US5237670A (en) * 1989-01-30 1993-08-17 Alantec, Inc. Method and apparatus for data transfer between source and destination modules
US5253352A (en) * 1989-11-13 1993-10-12 Zenith Data Systems Corporation Method and apparatus for pipelining cache accesses using anticipatory initiation of cache read
US5574868A (en) * 1993-05-14 1996-11-12 Intel Corporation Bus grant prediction technique for a split transaction bus in a multiprocessor computer system
US5430676A (en) * 1993-06-02 1995-07-04 Rambus, Inc. Dynamic random access memory system
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US5630096A (en) * 1995-05-10 1997-05-13 Microunity Systems Engineering, Inc. Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order
JP4014669B2 (ja) * 1996-04-22 2007-11-28 株式会社ルネサステクノロジ 同期型半導体記憶装置
US5835965A (en) * 1996-04-24 1998-11-10 Cirrus Logic, Inc. Memory system with multiplexed input-output port and memory mapping capability
KR100212142B1 (ko) * 1996-09-12 1999-08-02 윤종용 매크로 명령기능을 가진 동기식 반도체 메모리장치와 매크로 명령의 저장 및 실행방법
US5870350A (en) * 1997-05-21 1999-02-09 International Business Machines Corporation High performance, high bandwidth memory bus architecture utilizing SDRAMs

Also Published As

Publication number Publication date
US6065093A (en) 2000-05-16
DE69924179T2 (de) 2006-03-23
JP3384770B2 (ja) 2003-03-10
JP2000030452A (ja) 2000-01-28
KR100332188B1 (ko) 2002-04-12
KR19990087921A (ko) 1999-12-27
EP0957490A1 (de) 1999-11-17
EP0957490B1 (de) 2005-03-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: DUSCHER, R., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 7