DE69906348D1 - Speicher mit vektorzugriff - Google Patents

Speicher mit vektorzugriff

Info

Publication number
DE69906348D1
DE69906348D1 DE69906348T DE69906348T DE69906348D1 DE 69906348 D1 DE69906348 D1 DE 69906348D1 DE 69906348 T DE69906348 T DE 69906348T DE 69906348 T DE69906348 T DE 69906348T DE 69906348 D1 DE69906348 D1 DE 69906348D1
Authority
DE
Germany
Prior art keywords
memory
vector access
vector
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69906348T
Other languages
English (en)
Other versions
DE69906348T2 (de
Inventor
Alain Demeure
Didier Tomasini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales Underwater Systems SAS
Original Assignee
Thales Underwater Systems SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales Underwater Systems SAS filed Critical Thales Underwater Systems SAS
Application granted granted Critical
Publication of DE69906348D1 publication Critical patent/DE69906348D1/de
Publication of DE69906348T2 publication Critical patent/DE69906348T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
DE69906348T 1998-10-30 1999-10-22 Speicher mit vektorzugriff Expired - Fee Related DE69906348T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9813664A FR2785406B1 (fr) 1998-10-30 1998-10-30 Memoire a acces vectoriel
PCT/FR1999/002578 WO2000026790A1 (fr) 1998-10-30 1999-10-22 Memoire a acces vectoriel

Publications (2)

Publication Number Publication Date
DE69906348D1 true DE69906348D1 (de) 2003-04-30
DE69906348T2 DE69906348T2 (de) 2003-12-04

Family

ID=9532201

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69906348T Expired - Fee Related DE69906348T2 (de) 1998-10-30 1999-10-22 Speicher mit vektorzugriff

Country Status (6)

Country Link
US (1) US6704834B1 (de)
EP (1) EP1125205B1 (de)
JP (1) JP2002529814A (de)
DE (1) DE69906348T2 (de)
FR (1) FR2785406B1 (de)
WO (1) WO2000026790A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3532860B2 (ja) * 2001-01-22 2004-05-31 株式会社東芝 剰余系表現を利用した演算装置及び方法及びプログラム
US7933405B2 (en) * 2005-04-08 2011-04-26 Icera Inc. Data access and permute unit
DE602007011755D1 (de) * 2006-05-16 2011-02-17 Nxp Bv Speicherarchitektur
US8862827B2 (en) 2009-12-29 2014-10-14 International Business Machines Corporation Efficient multi-level software cache using SIMD vector permute functionality
US10223111B2 (en) * 2011-12-22 2019-03-05 Intel Corporation Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset
US10565283B2 (en) 2011-12-22 2020-02-18 Intel Corporation Processors, methods, systems, and instructions to generate sequences of consecutive integers in numerical order
CN108681465B (zh) * 2011-12-22 2022-08-02 英特尔公司 用于产生整数序列的处理器、处理器核及系统
WO2013095564A1 (en) 2011-12-22 2013-06-27 Intel Corporation Processors, methods, systems, and instructions to generate sequences of integers in numerical order that differ by a constant stride
US10180829B2 (en) * 2015-12-15 2019-01-15 Nxp Usa, Inc. System and method for modulo addressing vectorization with invariant code motion

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2457521B1 (fr) 1979-05-23 1985-12-27 Thomson Csf Systeme multiprocesseur de traitement de signal
FR2535067A1 (fr) 1982-10-22 1984-04-27 Thomson Csf Dispositif numerique de formation de voies sonar
US5394553A (en) * 1991-06-12 1995-02-28 Lee Research, Inc. High performance array processor with nonlinear skewing of elements
FR2732787B1 (fr) 1995-04-07 1997-05-16 Thomson Csf Procede de saisie graphique d'application de traitement de signal
FR2748138B1 (fr) 1996-04-26 1998-07-10 Thomson Csf Procede de codage pour processeur de traitement de signal, et processeur pour la mise en oeuvre d'un tel procede

Also Published As

Publication number Publication date
EP1125205A1 (de) 2001-08-22
EP1125205B1 (de) 2003-03-26
FR2785406B1 (fr) 2004-09-10
DE69906348T2 (de) 2003-12-04
WO2000026790A1 (fr) 2000-05-11
JP2002529814A (ja) 2002-09-10
US6704834B1 (en) 2004-03-09
FR2785406A1 (fr) 2000-05-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee