DE69839780D1 - Silizium auf eine isolator-konfiguration welche mit der massen-cmos-architektur kompatibel ist - Google Patents

Silizium auf eine isolator-konfiguration welche mit der massen-cmos-architektur kompatibel ist

Info

Publication number
DE69839780D1
DE69839780D1 DE69839780T DE69839780T DE69839780D1 DE 69839780 D1 DE69839780 D1 DE 69839780D1 DE 69839780 T DE69839780 T DE 69839780T DE 69839780 T DE69839780 T DE 69839780T DE 69839780 D1 DE69839780 D1 DE 69839780D1
Authority
DE
Germany
Prior art keywords
compatible
silicon
mass
cmos architecture
isolator configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69839780T
Other languages
German (de)
English (en)
Inventor
Donald L Wollesen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69839780D1 publication Critical patent/DE69839780D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
DE69839780T 1997-12-19 1998-12-18 Silizium auf eine isolator-konfiguration welche mit der massen-cmos-architektur kompatibel ist Expired - Lifetime DE69839780D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US99435597A 1997-12-19 1997-12-19
PCT/US1998/026846 WO1999033115A1 (en) 1997-12-19 1998-12-18 Silicon-on-insulator configuration which is compatible with bulk cmos architecture

Publications (1)

Publication Number Publication Date
DE69839780D1 true DE69839780D1 (de) 2008-09-04

Family

ID=25540571

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69839780T Expired - Lifetime DE69839780D1 (de) 1997-12-19 1998-12-18 Silizium auf eine isolator-konfiguration welche mit der massen-cmos-architektur kompatibel ist

Country Status (6)

Country Link
US (1) US6215155B1 (https=)
EP (1) EP1042811B1 (https=)
JP (1) JP2001527293A (https=)
KR (1) KR100562539B1 (https=)
DE (1) DE69839780D1 (https=)
WO (1) WO1999033115A1 (https=)

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KR100259097B1 (ko) * 1998-04-02 2000-06-15 김영환 반도체 소자 및 그의 제조 방법
TW444266B (en) * 1998-07-23 2001-07-01 Canon Kk Semiconductor substrate and method of producing same
US6274887B1 (en) * 1998-11-02 2001-08-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method therefor
US7141821B1 (en) * 1998-11-10 2006-11-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having an impurity gradient in the impurity regions and method of manufacture
US6277679B1 (en) 1998-11-25 2001-08-21 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing thin film transistor
JP3408762B2 (ja) * 1998-12-03 2003-05-19 シャープ株式会社 Ｓｏｉ構造の半導体装置及びその製造方法
JP2001111056A (ja) * 1999-10-06 2001-04-20 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6646287B1 (en) 1999-11-19 2003-11-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with tapered gate and insulating film
US6429099B1 (en) * 2000-01-05 2002-08-06 International Business Machines Corporation Implementing contacts for bodies of semiconductor-on-insulator transistors
US6287901B1 (en) * 2000-01-05 2001-09-11 International Business Machines Corporation Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors
TW476993B (en) * 2000-01-19 2002-02-21 Advanced Micro Devices Inc Silicon on insulator circuit structure with buried semiconductor interconnect structure and method for forming same
JP3472742B2 (ja) * 2000-03-31 2003-12-02 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
JP4776755B2 (ja) * 2000-06-08 2011-09-21 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
TW501227B (en) * 2000-08-11 2002-09-01 Samsung Electronics Co Ltd SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same
US6465331B1 (en) * 2000-08-31 2002-10-15 Micron Technology, Inc. DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines
JP2002076311A (ja) * 2000-09-01 2002-03-15 Seiko Epson Corp 半導体装置およびその製造方法
JP2002359310A (ja) * 2001-05-30 2002-12-13 Matsushita Electric Ind Co Ltd 半導体装置、及びその製造方法
KR100422468B1 (ko) * 2001-07-31 2004-03-11 삼성전자주식회사 에스 오 아이 소자 및 그 제조방법
US6498371B1 (en) 2001-07-31 2002-12-24 Advanced Micro Devices, Inc. Body-tied-to-body SOI CMOS inverter circuit
JP2003124345A (ja) * 2001-10-11 2003-04-25 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
DE10151132A1 (de) * 2001-10-17 2003-05-08 Infineon Technologies Ag Halbleiterstruktur mit einem von dem Substrat kapazitiv entkoppelten Bauelementen
JP4176342B2 (ja) * 2001-10-29 2008-11-05 川崎マイクロエレクトロニクス株式会社 半導体装置およびそのレイアウト方法
US6844224B2 (en) 2001-11-15 2005-01-18 Freescale Semiconductor, Inc. Substrate contact in SOI and method therefor
US20030134486A1 (en) * 2002-01-16 2003-07-17 Zhongze Wang Semiconductor-on-insulator comprising integrated circuitry
US7432136B2 (en) 2002-05-06 2008-10-07 Advanced Micro Devices, Inc. Transistors with controllable threshold voltages, and various methods of making and operating same
US7129142B2 (en) 2002-06-11 2006-10-31 Advanced Micro Devices, Inc. Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same
JP4850387B2 (ja) * 2002-12-09 2012-01-11 ルネサスエレクトロニクス株式会社 半導体装置
EP1588418A1 (de) 2003-01-30 2005-10-26 X-FAB Semiconductor Foundries AG Soi struktur mit substratkontakten beidseits der box und herstellungs-verfahren für eine solche struktur
JP4065855B2 (ja) * 2004-01-21 2008-03-26 株式会社日立製作所 生体および化学試料検査装置
JP4664631B2 (ja) * 2004-08-05 2011-04-06 株式会社東芝 半導体装置及びその製造方法
US6949768B1 (en) * 2004-10-18 2005-09-27 International Business Machines Corporation Planar substrate devices integrated with finfets and method of manufacture
US7244659B2 (en) * 2005-03-10 2007-07-17 Micron Technology, Inc. Integrated circuits and methods of forming a field effect transistor
US20100084709A1 (en) 2005-07-05 2010-04-08 Ryuta Tsuchiya Semiconductor device and method for manufacturing same
US20070023833A1 (en) * 2005-07-28 2007-02-01 Serguei Okhonin Method for reading a memory cell having an electrically floating body transistor, and memory cell and array implementing same
US20070252233A1 (en) * 2006-04-28 2007-11-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the semiconductor device
US7696562B2 (en) * 2006-04-28 2010-04-13 Semiconductor Energy Laboratory Co., Ltd Semiconductor device
US7557002B2 (en) 2006-08-18 2009-07-07 Micron Technology, Inc. Methods of forming transistor devices
US7989322B2 (en) 2007-02-07 2011-08-02 Micron Technology, Inc. Methods of forming transistors
JP6076224B2 (ja) 2013-09-05 2017-02-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9514987B1 (en) 2015-06-19 2016-12-06 International Business Machines Corporation Backside contact to final substrate
US9837412B2 (en) * 2015-12-09 2017-12-05 Peregrine Semiconductor Corporation S-contact for SOI
CN105680107B (zh) * 2016-03-16 2018-09-25 中国科学院上海微系统与信息技术研究所 一种基于soi工艺的电池管理芯片电路
JP6889441B2 (ja) 2017-03-10 2021-06-18 三菱重工業株式会社 半導体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463238A (en) * 1992-02-25 1995-10-31 Seiko Instruments Inc. CMOS structure with parasitic channel prevention
US5359219A (en) * 1992-12-04 1994-10-25 Texas Instruments Incorporated Silicon on insulator device comprising improved substrate doping
JPH0832040A (ja) * 1994-07-14 1996-02-02 Nec Corp 半導体装置
JP3462301B2 (ja) 1995-06-16 2003-11-05 三菱電機株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
EP1042811A1 (en) 2000-10-11
US6215155B1 (en) 2001-04-10
KR100562539B1 (ko) 2006-03-22
WO1999033115A1 (en) 1999-07-01
EP1042811B1 (en) 2008-07-23
JP2001527293A (ja) 2001-12-25
KR20010033347A (ko) 2001-04-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES, INC., GRAND CAYMANN, KY

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,