CN105680107B - 一种基于soi工艺的电池管理芯片电路 - Google Patents

一种基于soi工艺的电池管理芯片电路 Download PDF

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CN105680107B
CN105680107B CN201610150614.7A CN201610150614A CN105680107B CN 105680107 B CN105680107 B CN 105680107B CN 201610150614 A CN201610150614 A CN 201610150614A CN 105680107 B CN105680107 B CN 105680107B
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oxide
metal
semiconductor
battery management
management chip
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CN105680107A (zh
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程新红
李新昌
吴忠昊
徐大伟
羊志强
俞跃辉
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Shanghai Institute of Microsystem and Information Technology of CAS
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Abstract

本发明提供一种基于SOI工艺的电池管理芯片电路，所述电池管理芯片电路包括高压多路选通器MUX、电压基准电路、Sigma‑delta ADC（包括模拟调制器以及数字滤波器）、SPI通讯电路、以及功能控制电路与电压值寄存器。所述电池管理芯片电路为基于SOI高压工艺集成，尤其是所述电池管理芯片电路采用的高压MOS管为基于SOI工艺的高压MOS器件单元。另外，本发明重点突出了高压多路选通器MUX与Sigma‑delta ADC的接口电路‑斩波电路的设计，以阐述本发明采用SOI工艺设计与流片时会带来电路设计难度降低以及版图面积减小等诸多优势。

Description

一种基于SOI工艺的电池管理芯片电路
技术领域
本发明涉及一种电池管理芯片电路，特别是涉及一种基于SOI工艺的电池管理芯片电路。
背景技术
电动车未来将以锂电池为主要动力驱动来源，BMS(Battery Management System)电池管理系统是用来保障锂电池正常工作的关键部分，主要包括电池电压转换与量测电路、电池平衡驱动电路、开关驱动电路、电流量测、通讯电路，以及相应的后端数据处理模块。常见的BMS原理框图如图1所示。
由于BMS一般会涉及到高电压(0-60V)领域，该芯片的设计以及制造对半导体工艺有着相当高的要求。当前，市场上的BMS芯片的设计以及制造多采用高压BCD工艺，BCD工艺的各个集成电路器件单元采用硅衬底制备，器件单元间采用PN结隔离高压，图2所示为BCD工艺中一高压器件剖面图。
该高压器件在高压集成电路设计中对器件各个端口电压要求非常严格，一般而言，包括：1)PSUB端需要接GND电压；2)LDWELL端需要接高压(但是电压不能高出LDWELL与PSUB间的最大隔离电压值)；3)BULK端电压不能高于LDWELL，但也不能低于该PN结的反向隔离电压最大值；4)SOURCE端、DRAIN端、GATE端可视为悬浮于高压阱内的普通MOS器件。
根据上述介绍可知，BCD工艺中该类器件为6端器件。在电路设计中对各个端口电压要求极其严格，尤其是LDWELL与BULK两个端口为普通工艺所不常用，在芯片设计中需要认真考虑电压值，一旦考虑不周，抑或是仿真文件存在缺陷，仿真软件不会报错，芯片流片之后，就会存在高压漏电甚至击穿问题。这对于集成电路流片的高成本而言是难以接受的。
基于以上所述，提供一种隔离性能好、器件端口较少的BMS设计与制造工艺实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基于SOI工艺的电池管理芯片电路，用于解决现有技术中电池管理芯片电路隔离性能较差，端口较多，结构复杂的问题。
为实现上述目的及其他相关目的，本发明提供一种基于SOI工艺的电池管理芯片电路，所述电池管理芯片电路基于SOI高压工艺集成。
作为本发明的基于SOI工艺的电池管理芯片电路的一种优选方案，所述电池管理芯片电路采用的高压MOS管为基于SOI工艺的高压MOS器件单元。
作为本发明的基于SOI工艺的电池管理芯片电路的一种优选方案，所述基于SOI工艺的MOS器件单元包括：SOI衬底，包括硅衬底、绝缘层以及顶层硅；所述顶层硅中形成有NMOS器件或/及PMOS器件；所述NMOS器件形成于所述顶层硅的P阱区域，包括N+型源区、N+型漏区、栅极结构、P+型体区，所述P+型体区与N+型源区之间采用浅沟道结构隔离；所述PMOS器件形成于所述顶层硅的N阱区域，包括P+型源区、P+型漏区、栅极结构、N+型体区，所述N+型体区与P+型源区之间采用浅沟道结构隔离。
进一步地，所述基于SOI工艺的MOS器件单元包括NMOS器件及PMOS器件，且所述NMOS器件及PMOS器件之间采用浅沟道结构隔离。
作为本发明的基于SOI工艺的电池管理芯片电路的一种优选方案，所述NMOS器件包括分别对应于N+型源区、N+型漏区、栅极结构、P+型体区的4个引出端。
作为本发明的基于SOI工艺的电池管理芯片电路的一种优选方案，所述PMOS器件包括分别对应于P+型源区、P+型漏区、栅极结构、N+型体区的4个引出端。
作为本发明的基于SOI工艺的电池管理芯片电路的一种优选方案，所述基于SOI工艺的MOS器件单元之间采用深沟槽结构隔离，所述深沟槽结构包括至少贯穿所述顶层硅的深沟槽以及填充于所述深沟槽内的绝缘材料。
作为本发明的基于SOI工艺的电池管理芯片电路的一种优选方案，所述电池管理芯片电路的工作电压为0～60V。
作为本发明的基于SOI工艺的电池管理芯片电路的一种优选方案，所述电池管理芯片电路包括模拟调制器输入的接口电路，所述接口电路包括：基于SOI工艺集成的第一MOS管、第二MOS管、第三MOS管、第四MOS管、第一二极管、第二二极管、第一电容以及第二电容，其中，所述第一MOS管、第二MOS管、第三MOS管、第四MOS管的源端与第一二极管、第二二极管的正极相连，并与输入电压相连，所述第一MOS管的栅极、第四MOS管的栅极以及第三MOS管的漏极与第一二极管的负极以及第一电容的负极相连，所述第二MOS管、第三MOS管的栅极以及第四MOS管的漏极与第二二极管的负极以及第二电容的负极相连，所述第一电容及第二电容的正极分别连接非交叠互补时钟信号；所述第一MOS管及第二MOS管的漏极分别作为电路的输出端。
如上所述，本发明的基于SOI工艺的电池管理芯片电路，具有以下有益效果：
1)BCD工艺对称型高压MOS为六端器件，相应的SOI高压器件为4端器件，减小了芯片设计的难度以及风险，降低了版图设计的布线难度。
2)SOI工艺中深沟槽(TRENCH)结构用于隔离版图上的各个单元，TRENCH为绝缘层耐压能力强，相对于BCD工艺中PN结隔离要占用更小的芯片面积。
3)SOI中TRENCH隔离不存在BCD工艺中PN结隔离的漏电流，减小芯片的功耗。
4)此外，SOI本身还固有的一些优势包括：耐高温、抗闩锁，提高芯片的可靠性及稳定性；SOI器件能有效减少器件之间的串扰，具有一定的抗辐照性能，可以应用于更高频领域，使芯片具有更广的应用领域。
附图说明
图1显示为电池管理芯片电路的结构框图。
图2显示为现有技术中基于BCD工艺制备的高压器件的结构示意图。
图3显示为本发明的基于SOI工艺的MOS器件单元的结构示意图。
图4显示为本发明的模拟调制器输入的接口电路的电路结构示意图。
图5显示为本发明的模拟调制器输入的接口电路的仿真结果示意图。
元件标号说明
101 硅衬底
102 绝缘层
103 P阱区域
104 N+型源区
105 N+型漏区
106 栅极结构
107 P+型体区
108 浅沟道结构
109 N阱区域
110 P+型源区
111 P+型漏区
112 栅极结构
113 N+型体区
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1及图3～图5。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1及图3～图5所示，本实施例提供一种基于SOI工艺的电池管理芯片电路，如图1所示，本实施例的电池管理芯片电路包括：高压多路选通器MUX、电压基准电路、Sigma-delta ADC(包括模拟调制器以及数字滤波器)、SPI通讯电路、以及功能控制电路与电压值寄存器。在本实施例中，所述电池管理芯片电路基于SOI高压工艺集成。
作为示例，所述电池管理芯片电路采用的高压MOS管为基于SOI工艺的高压MOS器件单元。
如图3所示，作为示例，所述基于SOI工艺的MOS器件单元包括：SOI衬底，包括硅衬底101、绝缘层102以及顶层硅；所述顶层硅中形成有NMOS器件或/及PMOS器件；所述NMOS器件形成于所述顶层硅的P阱区域103，包括N+型源区104、N+型漏区105、栅极结构106、P+型体区107，所述P+型体区107与N+型源区104之间采用浅沟道结构108隔离；所述PMOS器件形成于所述顶层硅的N阱区域109，包括P+型源区110、P+型漏区111、栅极结构112、N+型体区113，所述N+型体区113与P+型源区110之间采用浅沟道结构108隔离。如图3所示，在本实施例中，所述基于SOI工艺的MOS器件单元包括NMOS器件及PMOS器件，且所述NMOS器件及PMOS器件之间采用浅沟道结构108隔离。
如图3所示，作为示例，所述NMOS器件包括分别对应于N+型源区104、N+型漏区105、栅极结构106、P+型体区107的4个引出端。
如图3所示，作为示例，所述PMOS器件包括分别对应于P+型源区110、P+型漏区111、栅极结构112、N+型体区113的4个引出端。
如图3所示，作为示例，所述基于SOI工艺的MOS器件单元之间采用深沟槽结构114隔离，所述深沟槽结构114包括至少贯穿所述顶层硅的深沟槽以及填充于所述深沟槽内的绝缘材料。被隔离的高压MOS器件单元之间的耐压由深沟槽结构114的耐压决定。由于SOI的衬底具有绝缘层，BULK端可以直接接高电压而不必再考虑类似于BCD工艺中的PN结隔离耐压问题。
作为示例，所述电池管理芯片电路的工作电压为0～60V。
在一个具体的实施过程中，所述电池管理芯片电路包括模拟调制器输入的接口电路，即多路选通器MUX与Sigma-delta ADC的接口电路，所述接口电路包括：基于SOI工艺集成的第一MOS管M1、第二MOS管M2、第三MOS管M3、第四MOS管M4、第一二极管D1、第二二极管D2、第一电容C1以及第二电容C2，其中，所述第一MOS管M1、第二MOS管M2、第三MOS管M3、第四MOS管M4的源端与第一二极管D1、第二二极管D2的正极相连，并与输入电压相连，所述第一MOS管M1的栅极、第四MOS管M4的栅极以及第三MOS管M3的漏极与第一二极管D1的负极以及第一电容C1的负极相连，所述第二MOS管M2、第三MOS管M3的栅极以及第四MOS管M4的漏极与第二二极管D2的负极以及第二电容C2的负极相连，所述第一电容C1及第二电容C2的正极分别连接非交叠互补时钟信号CLKB、CLKA；所述第一MOS管M1及第二MOS管M2的漏极分别作为电路的输出端。
在本实施例中，图4中各个器件在芯片工作过程中承受电压范围为0V～60V，即0V≦Pin≦60V，0V≦Nin≦60V。电压源Pin、Nin用于模拟图1中多路选通器(MUX)的输出。图4电路的仿真结果如图5所示。
当Pin＝60V，Nin＝55V时，如果器件M1-M4采用图2所示体硅结构，BULK端为55V，此时需要谨慎考虑LDWELL一端电压，根据P-well与Medium doped N-well间PN结反向耐压限制(工艺限制)，LDWELL接Pin电压为最佳选择。如果M1-M4采用图3所示SOI工艺高压器件，则不必考虑存在LDWELL一端的电压问题，减少芯片设计和版图布线的难度，增加芯片设计的可靠性。D1和D2为高压二极管在BCD工艺中，其N端同样需要有轻掺杂N阱用于高压隔离；如果采用SOI工艺则无需该轻掺杂N阱。
此外，图4所示电路中，BCD高压器件的电压隔离通常会占用较大的版图面积。根据某0.35μm BCD工艺库文件设计规则(图2所示)，仅LDWELL边界与PWELL边界最小尺寸为5μm，大大浪费了芯片的版图面积，增加成本。采用SOI工艺则会避免此芯片面积的开销，节约成本。
根据半导体器件物理的基本理论，PN结两端存在反向电压Vf时，BCD工艺中PN结会有微弱的漏电流Is。反向电流密度Js：
在SOI工艺中由于采用绝缘层结构，不会存在漏电现象。
如上所述，本发明的基于SOI工艺的电池管理芯片电路，具有以下有益效果：
1)BCD工艺对称型高压MOS为六端器件，相应的SOI高压器件为4端器件，减小了芯片设计的难度以及风险，降低了版图设计的布线难度。
2)SOI工艺中深沟槽(TRENCH)结构用于隔离版图上的各个单元，TRENCH为绝缘层耐压能力强，相对于BCD工艺中PN结隔离要占用更小的芯片面积。
3)SOI中TRENCH隔离不存在BCD工艺中PN结隔离的漏电流，减小芯片的功耗。
4)此外，SOI本身还固有的一些优势包括：耐高温、抗闩锁，提高芯片的可靠性及稳定性；SOI器件能有效减少器件之间的串扰，具有一定的抗辐照性能，可以应用于更高频领域，使芯片具有更广的应用领域。
所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (6)

1.一种基于SOI工艺的电池管理芯片电路，其特征在于，所述电池管理芯片电路基于SOI高压工艺集成，所述电池管理芯片电路采用的高压MOS管为基于SOI工艺的高压MOS器件单元，所述基于SOI工艺的高压MOS器件单元包括：
SOI衬底，包括硅衬底、绝缘层以及顶层硅；所述顶层硅中形成有NMOS器件或/及PMOS器件；
所述NMOS器件形成于所述顶层硅的P阱区域，包括N+型源区、N+型漏区、栅极结构、P+型体区，所述P+型体区与N+型源区之间采用浅沟道结构隔离；
所述PMOS器件形成于所述顶层硅的N阱区域，包括P+型源区、P+型漏区、栅极结构、N+型体区，所述N+型体区与P+型源区之间采用浅沟道结构隔离，
所述基于SOI工艺的MOS器件单元之间采用深沟槽结构隔离，所述深沟槽结构包括至少贯穿所述顶层硅的深沟槽以及填充于所述深沟槽内的绝缘材料。
2.根据权利要求1所述的基于SOI工艺的电池管理芯片电路，其特征在于：所述基于SOI工艺的MOS器件单元包括NMOS器件及PMOS器件，且所述NMOS器件及PMOS器件之间采用浅沟道结构隔离。
3.根据权利要求1所述的基于SOI工艺的电池管理芯片电路，其特征在于：所述NMOS器件包括分别对应于N+型源区、N+型漏区、栅极结构、P+型体区的4个引出端。
4.根据权利要求1所述的基于SOI工艺的电池管理芯片电路，其特征在于：所述PMOS器件包括分别对应于P+型源区、P+型漏区、栅极结构、N+型体区的4个引出端。
5.根据权利要求1所述的基于SOI工艺的电池管理芯片电路，其特征在于：所述电池管理芯片电路的工作电压为0～60V。
6.根据权利要求1～5任意一项所述的基于SOI工艺的电池管理芯片电路，其特征在于：所述电池管理芯片电路包括模拟调制器输入的接口电路，所述接口电路包括：基于SOI工艺集成的第一MOS管、第二MOS管、第三MOS管、第四MOS管、第一二极管、第二二极管、第一电容以及第二电容，其中，所述第一MOS管、第二MOS管、第三MOS管、第四MOS管的源端与第一二极管、第二二极管的正极相连，并与输入电压相连，所述第一MOS管的栅极、第四MOS管的栅极以及第三MOS管的漏极与第一二极管的负极以及第一电容的负极相连，所述第二MOS管、第三MOS管的栅极以及第四MOS管的漏极与第二二极管的负极以及第二电容的负极相连，所述第一电容及第二电容的正极分别连接非交叠互补时钟信号；所述第一MOS管及第二MOS管的漏极分别作为电路的输出端。
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