DE69836941D1 - Herstellungsverfahren für MOS-Struktur mit asymetrisch-dotiertem Kanal - Google Patents
Herstellungsverfahren für MOS-Struktur mit asymetrisch-dotiertem KanalInfo
- Publication number
- DE69836941D1 DE69836941D1 DE69836941T DE69836941T DE69836941D1 DE 69836941 D1 DE69836941 D1 DE 69836941D1 DE 69836941 T DE69836941 T DE 69836941T DE 69836941 T DE69836941 T DE 69836941T DE 69836941 D1 DE69836941 D1 DE 69836941D1
- Authority
- DE
- Germany
- Prior art keywords
- asymmetrically
- manufacturing
- mos structure
- doped channel
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/918,678 US5891782A (en) | 1997-08-21 | 1997-08-21 | Method for fabricating an asymmetric channel doped MOS structure |
US918678 | 1997-08-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69836941D1 true DE69836941D1 (de) | 2007-03-15 |
DE69836941T2 DE69836941T2 (de) | 2007-10-18 |
Family
ID=25440770
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69836941T Expired - Fee Related DE69836941T2 (de) | 1997-08-21 | 1998-08-05 | Herstellungsverfahren für MOS-Struktur mit asymetrisch-dotiertem Kanal |
Country Status (6)
Country | Link |
---|---|
US (1) | US5891782A (de) |
EP (2) | EP1605501A1 (de) |
JP (1) | JPH1197709A (de) |
KR (1) | KR100276775B1 (de) |
DE (1) | DE69836941T2 (de) |
TW (1) | TW447024B (de) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6027978A (en) * | 1997-01-28 | 2000-02-22 | Advanced Micro Devices, Inc. | Method of making an IGFET with a non-uniform lateral doping profile in the channel region |
JP4242461B2 (ja) * | 1997-02-24 | 2009-03-25 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US6605845B1 (en) * | 1997-09-30 | 2003-08-12 | Intel Corporation | Asymmetric MOSFET using spacer gate technique |
US6180983B1 (en) * | 1998-07-17 | 2001-01-30 | National Semiconductor Corporation | High-voltage MOS transistor on a silicon on insulator wafer |
US6291325B1 (en) * | 1998-11-18 | 2001-09-18 | Sharp Laboratories Of America, Inc. | Asymmetric MOS channel structure with drain extension and method for same |
US6482724B1 (en) * | 1999-09-07 | 2002-11-19 | Texas Instruments Incorporated | Integrated circuit asymmetric transistors |
KR100374551B1 (ko) * | 2000-01-27 | 2003-03-04 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조방법 |
US6667512B1 (en) | 2000-01-28 | 2003-12-23 | Advanced Micro Devices, Inc. | Asymmetric retrograde halo metal-oxide-semiconductor field-effect transistor (MOSFET) |
US6274441B1 (en) | 2000-04-27 | 2001-08-14 | International Business Machines Corporation | Method of forming bitline diffusion halo under gate conductor ledge |
US7217977B2 (en) * | 2004-04-19 | 2007-05-15 | Hrl Laboratories, Llc | Covert transformation of transistor properties as a circuit protection method |
SE519382C2 (sv) | 2000-11-03 | 2003-02-25 | Ericsson Telefon Ab L M | Integrering av självinriktade MOS-högspänningskomponenter samt halvledarstruktur innefattande sådana |
US6803317B2 (en) * | 2002-08-16 | 2004-10-12 | Semiconductor Components Industries, L.L.C. | Method of making a vertical gate semiconductor device |
US7049667B2 (en) | 2002-09-27 | 2006-05-23 | Hrl Laboratories, Llc | Conductive channel pseudo block process and circuit to inhibit reverse engineering |
AU2003293540A1 (en) * | 2002-12-13 | 2004-07-09 | Raytheon Company | Integrated circuit modification using well implants |
US7242063B1 (en) | 2004-06-29 | 2007-07-10 | Hrl Laboratories, Llc | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable |
US8168487B2 (en) * | 2006-09-28 | 2012-05-01 | Hrl Laboratories, Llc | Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer |
WO2010085241A1 (en) * | 2009-01-20 | 2010-07-29 | Hewlett-Packard Development Company, L.P. | Multilayer memristive devices |
US8895327B1 (en) | 2011-12-09 | 2014-11-25 | Suvolta, Inc. | Tipless transistors, short-tip transistors, and methods and circuits therefor |
US9653617B2 (en) | 2015-05-27 | 2017-05-16 | Sandisk Technologies Llc | Multiple junction thin film transistor |
CN113066857A (zh) * | 2021-03-24 | 2021-07-02 | 中国科学技术大学 | 高品质因数氧化镓晶体管及其制备方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0479424U (de) * | 1990-11-23 | 1992-07-10 | ||
EP0588370A3 (en) * | 1992-09-18 | 1994-06-08 | Matsushita Electric Ind Co Ltd | Manufacturing method of thin film transistor and semiconductor device utilized for liquid crystal display |
JP3343968B2 (ja) * | 1992-12-14 | 2002-11-11 | ソニー株式会社 | バイポーラ型半導体装置およびその製造方法 |
JPH07106512A (ja) * | 1993-10-04 | 1995-04-21 | Sharp Corp | 分子イオン注入を用いたsimox処理方法 |
US5401982A (en) * | 1994-03-03 | 1995-03-28 | Xerox Corporation | Reducing leakage current in a thin-film transistor with charge carrier densities that vary in two dimensions |
TW304301B (de) * | 1994-12-01 | 1997-05-01 | At & T Corp | |
US5510279A (en) * | 1995-01-06 | 1996-04-23 | United Microelectronics Corp. | Method of fabricating an asymmetric lightly doped drain transistor device |
JP3193845B2 (ja) * | 1995-05-24 | 2001-07-30 | シャープ株式会社 | 半導体装置及びその製造方法 |
US5985708A (en) * | 1996-03-13 | 1999-11-16 | Kabushiki Kaisha Toshiba | Method of manufacturing vertical power device |
-
1997
- 1997-08-21 US US08/918,678 patent/US5891782A/en not_active Expired - Fee Related
-
1998
- 1998-07-10 JP JP10195720A patent/JPH1197709A/ja active Pending
- 1998-07-31 TW TW087112634A patent/TW447024B/zh not_active IP Right Cessation
- 1998-08-05 EP EP05016748A patent/EP1605501A1/de not_active Ceased
- 1998-08-05 EP EP98306253A patent/EP0898304B1/de not_active Expired - Lifetime
- 1998-08-05 DE DE69836941T patent/DE69836941T2/de not_active Expired - Fee Related
- 1998-08-21 KR KR1019980033933A patent/KR100276775B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW447024B (en) | 2001-07-21 |
DE69836941T2 (de) | 2007-10-18 |
EP0898304A2 (de) | 1999-02-24 |
EP0898304B1 (de) | 2007-01-24 |
US5891782A (en) | 1999-04-06 |
KR19990023765A (ko) | 1999-03-25 |
JPH1197709A (ja) | 1999-04-09 |
KR100276775B1 (ko) | 2001-03-02 |
EP0898304A3 (de) | 2000-06-14 |
EP1605501A1 (de) | 2005-12-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |