DE69826744D1 - Mustergenerator mit erweiterter Registerprogrammierung - Google Patents

Mustergenerator mit erweiterter Registerprogrammierung

Info

Publication number
DE69826744D1
DE69826744D1 DE69826744T DE69826744T DE69826744D1 DE 69826744 D1 DE69826744 D1 DE 69826744D1 DE 69826744 T DE69826744 T DE 69826744T DE 69826744 T DE69826744 T DE 69826744T DE 69826744 D1 DE69826744 D1 DE 69826744D1
Authority
DE
Germany
Prior art keywords
pattern generator
extended register
register programming
programming
extended
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69826744T
Other languages
English (en)
Other versions
DE69826744T8 (de
DE69826744T2 (de
Inventor
Martin H Eastburn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Schlumberger Technologies Inc
Original Assignee
Schlumberger Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Schlumberger Technologies Inc filed Critical Schlumberger Technologies Inc
Publication of DE69826744D1 publication Critical patent/DE69826744D1/de
Application granted granted Critical
Publication of DE69826744T2 publication Critical patent/DE69826744T2/de
Publication of DE69826744T8 publication Critical patent/DE69826744T8/de
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31813—Test pattern generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69826744T 1997-02-18 1998-02-17 Mustergenerator mit erweiterter Registerprogrammierung Expired - Fee Related DE69826744T8 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/801,687 US5883905A (en) 1997-02-18 1997-02-18 Pattern generator with extended register programming
US801687 1997-02-18

Publications (3)

Publication Number Publication Date
DE69826744D1 true DE69826744D1 (de) 2004-11-11
DE69826744T2 DE69826744T2 (de) 2006-02-16
DE69826744T8 DE69826744T8 (de) 2006-04-27

Family

ID=25181798

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69826744T Expired - Fee Related DE69826744T8 (de) 1997-02-18 1998-02-17 Mustergenerator mit erweiterter Registerprogrammierung

Country Status (6)

Country Link
US (1) US5883905A (de)
EP (1) EP0859367B1 (de)
JP (1) JPH10275091A (de)
KR (1) KR19980071411A (de)
DE (1) DE69826744T8 (de)
TW (1) TW371324B (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3233068B2 (ja) * 1997-05-23 2001-11-26 安藤電気株式会社 パターン発生装置
US6073263A (en) * 1997-10-29 2000-06-06 Credence Systems Corporation Parallel processing pattern generation system for an integrated circuit tester
US6161206A (en) * 1998-04-30 2000-12-12 Credence Systems Corporation Pattern generator for a semiconductor integrated circuit tester
DE69902221T2 (de) 1999-02-23 2003-03-06 Taiwan Semiconductor Mfg Speicherschaltungen mit eingebautem Selbsttest
DE69901534T2 (de) * 1999-02-23 2003-01-09 Taiwan Semiconductor Mfg Integrierte Selbsttestschaltung für eine Speichereinrichtung
US6321356B1 (en) * 1999-05-18 2001-11-20 Micron Technology, Inc. Programmable pattern generator
US6425103B1 (en) * 1999-09-29 2002-07-23 Lsi Logic Corporation Programmable moving inversion sequencer for memory bist address generation
US6671845B1 (en) * 1999-10-19 2003-12-30 Schlumberger Technologies, Inc. Packet-based device test system
US6571365B1 (en) * 1999-11-03 2003-05-27 Unisys Corporation Initial stage of a multi-stage algorithmic pattern generator for testing IC chips
US6415408B1 (en) * 1999-11-03 2002-07-02 Unisys Corporation Multi-stage algorithmic pattern generator for testing IC chips
US6314034B1 (en) * 2000-04-14 2001-11-06 Advantest Corp. Application specific event based semiconductor memory test system
JP4146986B2 (ja) * 2000-05-19 2008-09-10 株式会社アドバンテスト 半導体試験装置
JP2002123562A (ja) * 2000-07-31 2002-04-26 Hitachi Ltd テスタ構築データの生成方法およびテスタの構築方法並びにテスト回路
JP2002071766A (ja) * 2000-08-28 2002-03-12 Advantest Corp 半導体試験装置
US6598112B1 (en) * 2000-09-11 2003-07-22 Agilent Technologies, Inc. Method and apparatus for executing a program using primary, secondary and tertiary memories
DE10111440C2 (de) * 2001-03-09 2003-02-20 Infineon Technologies Ag Adressengenerator zur Erzeugung von Adressen zum Testen einer Schaltung
US7143326B2 (en) * 2001-03-20 2006-11-28 Credence Systems Corporation Test system algorithmic program generators
KR100379721B1 (ko) * 2001-05-23 2003-04-10 송동섭 경계주사 테스트용 테스트벡터의 생성방법
US20030099139A1 (en) * 2001-08-24 2003-05-29 Abrosimov Igor Anatolievich Memory test apparatus and method of testing
WO2003093845A2 (en) * 2002-05-06 2003-11-13 Nextest Systems Corporation Semiconductor test system having multitasking algorithmic pattern generator
DE10231176A1 (de) * 2002-07-09 2003-10-30 Infineon Technologies Ag Testmustergeneratorschaltung
EP1554653B1 (de) * 2002-10-15 2011-08-24 STMicroelectronics S.A. Übertragung von wiederholungsdigitalnachrichten zwischen einer überwachungsschaltung eines mikroprozessors und eines analysewerkzeugs
US20060174155A1 (en) * 2005-02-03 2006-08-03 Arm Limited System, method and computer program product for testing software
US20090307468A1 (en) * 2008-06-06 2009-12-10 International Business Machines Corporation Generating a Test Case Micro Generator During Processor Design Verification and Validation
US8516305B2 (en) * 2010-09-01 2013-08-20 Advanced Micro Devices, Inc. Power dissipation test method and device therefor
FR2971872B1 (fr) * 2011-02-18 2014-06-20 Bull Sas Circuit integre programmable de cryptographie
US9195261B2 (en) 2013-09-03 2015-11-24 Teradyne, Inc. Synchronizing data from different clock domains by bridges one of the clock signals to appear to run an integer of cycles more than the other clock signal
US20170045981A1 (en) 2015-08-10 2017-02-16 Apple Inc. Devices and Methods for Processing Touch Inputs Based on Their Intensities
KR102314419B1 (ko) * 2021-07-27 2021-10-19 (주) 에이블리 반도체 테스트 패턴 발생 장치 및 방법
CN117037893A (zh) * 2023-10-08 2023-11-10 悦芯科技股份有限公司 一种用于存储芯片测试机向量产生器的微处理器系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293950A (en) * 1978-04-03 1981-10-06 Nippon Telegraph And Telephone Public Corporation Test pattern generating apparatus
US4313200A (en) * 1978-08-28 1982-01-26 Takeda Riken Kogyo Kabushikikaisha Logic test system permitting test pattern changes without dummy cycles
JPH0750159B2 (ja) * 1985-10-11 1995-05-31 株式会社日立製作所 テストパタ−ン発生装置
US4682330A (en) * 1985-10-11 1987-07-21 International Business Machines Corporation Hierarchical test system architecture
US4931723A (en) * 1985-12-18 1990-06-05 Schlumberger Technologies, Inc. Automatic test system having a "true tester-per-pin" architecture
JPH0255331U (de) * 1988-10-11 1990-04-20
US5151903A (en) * 1989-09-28 1992-09-29 Texas Instruments Incorporated High efficiency pattern sequence controller for automatic test equipment
DE4305442C2 (de) * 1993-02-23 1999-08-05 Hewlett Packard Gmbh Verfahren und Vorrichtung zum Erzeugen eines Testvektors
JPH0862302A (ja) * 1994-08-19 1996-03-08 Advantest Corp サイクル遅延用パターン発生器

Also Published As

Publication number Publication date
EP0859367A2 (de) 1998-08-19
EP0859367A3 (de) 1998-11-18
TW371324B (en) 1999-10-01
EP0859367B1 (de) 2004-10-06
DE69826744T8 (de) 2006-04-27
KR19980071411A (ko) 1998-10-26
US5883905A (en) 1999-03-16
JPH10275091A (ja) 1998-10-13
DE69826744T2 (de) 2006-02-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee