DE69815988T2 - Übertragungsvorrichtung zwischen mehreren Prozessoren - Google Patents

Übertragungsvorrichtung zwischen mehreren Prozessoren Download PDF

Info

Publication number
DE69815988T2
DE69815988T2 DE69815988T DE69815988T DE69815988T2 DE 69815988 T2 DE69815988 T2 DE 69815988T2 DE 69815988 T DE69815988 T DE 69815988T DE 69815988 T DE69815988 T DE 69815988T DE 69815988 T2 DE69815988 T2 DE 69815988T2
Authority
DE
Germany
Prior art keywords
local
bus
memory
external bus
several processors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69815988T
Other languages
English (en)
Other versions
DE69815988D1 (de
Inventor
Pierre Cornillon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Original Assignee
Alcatel SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SA filed Critical Alcatel SA
Publication of DE69815988D1 publication Critical patent/DE69815988D1/de
Application granted granted Critical
Publication of DE69815988T2 publication Critical patent/DE69815988T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
DE69815988T 1997-10-16 1998-10-15 Übertragungsvorrichtung zwischen mehreren Prozessoren Expired - Fee Related DE69815988T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9712960A FR2770008B1 (fr) 1997-10-16 1997-10-16 Dispositif de communication entre plusieurs processeurs

Publications (2)

Publication Number Publication Date
DE69815988D1 DE69815988D1 (de) 2003-08-07
DE69815988T2 true DE69815988T2 (de) 2004-01-15

Family

ID=9512303

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69815988T Expired - Fee Related DE69815988T2 (de) 1997-10-16 1998-10-15 Übertragungsvorrichtung zwischen mehreren Prozessoren

Country Status (5)

Country Link
EP (1) EP0910021B1 (de)
AT (1) ATE244419T1 (de)
DE (1) DE69815988T2 (de)
ES (1) ES2198670T3 (de)
FR (1) FR2770008B1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6295571B1 (en) * 1999-03-19 2001-09-25 Times N Systems, Inc. Shared memory apparatus and method for multiprocessor systems
US7136958B2 (en) 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US7788451B2 (en) 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7257683B2 (en) 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US6980042B2 (en) 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7363419B2 (en) 2004-05-28 2008-04-22 Micron Technology, Inc. Method and system for terminating write commands in a hub-based memory system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719621A (en) * 1985-07-15 1988-01-12 Raytheon Company Packet fastbus
AU598101B2 (en) * 1987-02-27 1990-06-14 Honeywell Bull Inc. Shared memory controller arrangement
JPH034351A (ja) * 1989-04-26 1991-01-10 Dubner Computer Syst Inc システム・バス・データ・リンク装置
US5664152A (en) * 1995-06-06 1997-09-02 Hewlett-Packard Company Multiple segmenting of main memory to streamline data paths in a computing system
US5734850A (en) * 1995-07-05 1998-03-31 National Semiconductor Corporation Transparent bridge between of a computer system and a method of interfacing the buses to operate as a single logical bus

Also Published As

Publication number Publication date
DE69815988D1 (de) 2003-08-07
FR2770008B1 (fr) 2001-10-12
EP0910021B1 (de) 2003-07-02
FR2770008A1 (fr) 1999-04-23
ES2198670T3 (es) 2004-02-01
EP0910021A1 (de) 1999-04-21
ATE244419T1 (de) 2003-07-15

Similar Documents

Publication Publication Date Title
DE69627240D1 (de) Synchronisierte Datenübermittlung zwischen Einheiten eines Verarbeitungssystems
NO993483L (no) Fremgangsmåte og anordning for effektiv overföring av datapakker
JPS54129942A (en) Direct transfer system between sub-systems
WO2001024031A3 (en) Multiprocessor node controller circuit and method
WO1998043148A3 (en) Novel multiprocessor distributed memory system and board and methods therefor
KR950013120A (ko) 계산기간 통신을 위한 통신제어장치 및 그것에 사용하는 집적회로
KR920006858A (ko) 직접 메모리 억세스 테이타 전송중의 버스 중재 최적화 방법 및 장치
DE69934226D1 (de) TCP/IP/PPP Modem
KR870006478A (ko) 네트워크 인터페이스 장치
EP0321156A3 (de) Datenübertragungssteuerungsvorrichtung
DE69815988D1 (de) Übertragungsvorrichtung zwischen mehreren Prozessoren
FR2800952B1 (fr) Architecture d'un circuit de chiffrement mettant en oeuvre differents types d'algorithmes de chiffrement simultanement sans perte de performance
KR850002914A (ko) 멀티 프로세서 시스템용 메세지 배향식 인터럽트 장치
DK0936562T3 (da) Fremgangsmåde og edb-system til kommunikation med mindst ét andet edb-system
JPS63192150A (ja) デ−タ転送緩衝装置
KR100210813B1 (ko) 전전자 교환기의 패킷 핸들러 리셋 장치
JPS54140439A (en) Composite computer device
KR100308146B1 (ko) 음성인식시스템의메시지처리방법
JP2875333B2 (ja) 子プロセッサへの初期データ設定方式
JPS5667429A (en) Information processing system
JPS61260350A (ja) 並列処理制御方式
DE69637321D1 (de) Weglenkereinheit für Nachrichtenweglenkungen in einem Verarbeitungssystem
JPH06110795A (ja) 監視タイマシステム
KR940009855A (ko) 통신 장치 및 방법
WO2001033363A3 (de) Bus-system zur simultanen bearbeitung verschiedener speicherzugriffe bei system-on-chip-lösungen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ALCATEL LUCENT, PARIS, FR

8339 Ceased/non-payment of the annual fee