DE69720092D1 - Mehrchipmodul - Google Patents
MehrchipmodulInfo
- Publication number
- DE69720092D1 DE69720092D1 DE69720092T DE69720092T DE69720092D1 DE 69720092 D1 DE69720092 D1 DE 69720092D1 DE 69720092 T DE69720092 T DE 69720092T DE 69720092 T DE69720092 T DE 69720092T DE 69720092 D1 DE69720092 D1 DE 69720092D1
- Authority
- DE
- Germany
- Prior art keywords
- chip module
- chip
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
- G01R31/318513—Test of Multi-Chip-Moduls
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/638,414 US5625631A (en) | 1996-04-26 | 1996-04-26 | Pass through mode for multi-chip-module die |
US638414 | 1996-04-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69720092D1 true DE69720092D1 (de) | 2003-04-30 |
DE69720092T2 DE69720092T2 (de) | 2004-02-26 |
Family
ID=24559927
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69720092T Expired - Fee Related DE69720092T2 (de) | 1996-04-26 | 1997-04-07 | Mehrchipmodul |
Country Status (4)
Country | Link |
---|---|
US (1) | US5625631A (de) |
EP (1) | EP0803735B1 (de) |
JP (1) | JP3111037B2 (de) |
DE (1) | DE69720092T2 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6480817B1 (en) * | 1994-09-01 | 2002-11-12 | Hynix Semiconductor, Inc. | Integrated circuit I/O pad cell modeling |
WO2005069025A1 (en) * | 2004-01-13 | 2005-07-28 | Koninklijke Philips Electronics N.V. | Jtag test architecture for multi-chip pack |
KR100790172B1 (ko) * | 2005-05-02 | 2007-12-31 | 삼성전자주식회사 | 시스템 인 패키지(SiP) 형태로 내장된 내부 롬에 고속프로그램 다운로드를 위한 칩 구현 방법 및 장치 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5483341A (en) * | 1977-12-15 | 1979-07-03 | Nec Corp | Digital integrated circuit |
JPS6188538A (ja) * | 1984-10-05 | 1986-05-06 | Fujitsu Ltd | 半導体装置 |
JP2601792B2 (ja) * | 1985-05-15 | 1997-04-16 | 株式会社東芝 | 大規模集積回路装置 |
JPS62220879A (ja) * | 1986-03-22 | 1987-09-29 | Hitachi Ltd | 半導体装置 |
US5365165A (en) * | 1986-09-19 | 1994-11-15 | Actel Corporation | Testability architecture and techniques for programmable interconnect architecture |
US5223792A (en) * | 1986-09-19 | 1993-06-29 | Actel Corporation | Testability architecture and techniques for programmable interconnect architecture |
JP2659095B2 (ja) * | 1987-06-30 | 1997-09-30 | 富士通株式会社 | ゲートアレイ及びメモリを有する半導体集積回路装置 |
JPH03180936A (ja) * | 1989-12-08 | 1991-08-06 | Matsushita Electric Ind Co Ltd | 内部バスのテスト回路 |
US5132571A (en) * | 1990-08-01 | 1992-07-21 | Actel Corporation | Programmable interconnect architecture having interconnects disposed above function modules |
US5191241A (en) * | 1990-08-01 | 1993-03-02 | Actel Corporation | Programmable interconnect architecture |
US5204556A (en) * | 1991-05-06 | 1993-04-20 | Lattice Semiconductor Corporation | Programmable interconnect structure for logic blocks |
KR930009704B1 (ko) * | 1991-09-07 | 1993-10-08 | 재단법인 한국전자통신연구소 | 칩선택 단자쌍(chip select pair)을 구비한 반도체장치 |
US5231312A (en) * | 1992-03-12 | 1993-07-27 | Atmel Corporation | Integrated logic circuit with functionally flexible input/output macrocells |
US5379308A (en) * | 1992-04-20 | 1995-01-03 | Intel Corporation | Apparatus for a bus-based integrated circuit test architecture |
-
1996
- 1996-04-26 US US08/638,414 patent/US5625631A/en not_active Expired - Fee Related
-
1997
- 1997-04-07 DE DE69720092T patent/DE69720092T2/de not_active Expired - Fee Related
- 1997-04-07 EP EP97302377A patent/EP0803735B1/de not_active Expired - Lifetime
- 1997-04-21 JP JP09103019A patent/JP3111037B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0803735B1 (de) | 2003-03-26 |
EP0803735A1 (de) | 1997-10-29 |
JPH1048287A (ja) | 1998-02-20 |
JP3111037B2 (ja) | 2000-11-20 |
US5625631A (en) | 1997-04-29 |
DE69720092T2 (de) | 2004-02-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |