DE69707677T2 - Verzögerungsschaltung und -verfahren - Google Patents

Verzögerungsschaltung und -verfahren

Info

Publication number
DE69707677T2
DE69707677T2 DE69707677T DE69707677T DE69707677T2 DE 69707677 T2 DE69707677 T2 DE 69707677T2 DE 69707677 T DE69707677 T DE 69707677T DE 69707677 T DE69707677 T DE 69707677T DE 69707677 T2 DE69707677 T2 DE 69707677T2
Authority
DE
Germany
Prior art keywords
delay circuit
delay
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69707677T
Other languages
English (en)
Other versions
DE69707677D1 (de
Inventor
B Anderson
A Tabor
J Jander
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Publication of DE69707677D1 publication Critical patent/DE69707677D1/de
Application granted granted Critical
Publication of DE69707677T2 publication Critical patent/DE69707677T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE69707677T 1996-06-28 1997-06-23 Verzögerungsschaltung und -verfahren Expired - Lifetime DE69707677T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/672,784 US6115769A (en) 1996-06-28 1996-06-28 Method and apparatus for providing precise circuit delays
PCT/GB1997/001688 WO1998000917A1 (en) 1996-06-28 1997-06-23 Delay circuit and method

Publications (2)

Publication Number Publication Date
DE69707677D1 DE69707677D1 (de) 2001-11-29
DE69707677T2 true DE69707677T2 (de) 2002-05-08

Family

ID=24699985

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69707677T Expired - Lifetime DE69707677T2 (de) 1996-06-28 1997-06-23 Verzögerungsschaltung und -verfahren

Country Status (5)

Country Link
US (2) US6115769A (de)
EP (1) EP0908013B1 (de)
AU (1) AU3184797A (de)
DE (1) DE69707677T2 (de)
WO (1) WO1998000917A1 (de)

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US6593789B2 (en) * 2001-12-14 2003-07-15 International Business Machines Corporation Precise and programmable duty cycle generator
US6657889B1 (en) 2002-06-28 2003-12-02 Motorola, Inc. Memory having write current ramp rate control
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US6856558B1 (en) * 2002-09-20 2005-02-15 Integrated Device Technology, Inc. Integrated circuit devices having high precision digital delay lines therein
US6850106B1 (en) * 2003-07-08 2005-02-01 Mohan Krishna Kunanayagam Voltage controlled oscillator delay cell
US7225349B2 (en) 2003-07-25 2007-05-29 Intel Corporation Power supply voltage droop compensated clock modulation for microprocessors
KR100509357B1 (ko) * 2003-08-08 2005-08-22 삼성전자주식회사 온도 독립형 전압 제어 발진기 및 주파수 발생 방법
US6891774B1 (en) 2003-09-03 2005-05-10 T-Ram, Inc. Delay line and output clock generator using same
US6958635B2 (en) * 2003-10-14 2005-10-25 Qualcomm Incorporated Low-power direct digital synthesizer with analog interpolation
US7817674B2 (en) * 2004-01-09 2010-10-19 Vitesse Semiconductor Corporation Output clock adjustment for a digital I/O between physical layer device and media access controller
US7464283B2 (en) * 2004-06-28 2008-12-09 Texas Instruments Incorporated System and method for producing precision timing signals by controlling register banks to provide a phase difference between two signal paths
US20060095221A1 (en) * 2004-11-03 2006-05-04 Teradyne, Inc. Method and apparatus for controlling variable delays in electronic circuitry
TWI312238B (en) * 2006-04-24 2009-07-11 Ind Tech Res Inst Delay line and analog-to-digital converting apparatus and load-sensing circuit using the same
US8099619B2 (en) 2006-09-28 2012-01-17 Intel Corporation Voltage regulator with drive override
JP2008135835A (ja) * 2006-11-27 2008-06-12 Fujitsu Ltd Ｐｌｌ回路
US9401799B2 (en) * 2014-08-04 2016-07-26 Stmicroelectronics S.R.L. Synchronization method, and corresponding device and integrated circuit
US11489518B2 (en) * 2021-03-05 2022-11-01 Qualcomm Incorporated Inverter-based delay element with adjustable current source/sink to reduce delay sensitivity to process and supply voltage variation

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US4902986B1 (en) * 1989-01-30 1998-09-01 Credence Systems Corp Phased locked loop to provide precise frequency and phase tracking of two signals
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US5389843A (en) * 1992-08-28 1995-02-14 Tektronix, Inc. Simplified structure for programmable delays
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US5400370A (en) * 1993-02-24 1995-03-21 Advanced Micro Devices Inc. All digital high speed algorithmic data recovery method and apparatus using locally generated compensated broad band time rulers and data edge position averaging
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US5533072A (en) * 1993-11-12 1996-07-02 International Business Machines Corporation Digital phase alignment and integrated multichannel transceiver employing same
JPH07154381A (ja) * 1993-11-30 1995-06-16 Hitachi Ltd データ転送装置
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Also Published As

Publication number Publication date
WO1998000917A1 (en) 1998-01-08
DE69707677D1 (de) 2001-11-29
AU3184797A (en) 1998-01-21
EP0908013B1 (de) 2001-10-24
US6115769A (en) 2000-09-05
EP0908013A1 (de) 1999-04-14
US6243784B1 (en) 2001-06-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: FIENER, J., PAT.-ANW., 87719 MINDELHEIM