KR970004866A - 디지탈 신호의 지연방법 및 회로 - Google Patents

디지탈 신호의 지연방법 및 회로 Download PDF

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Publication number
KR970004866A
KR970004866A KR1019950016155A KR19950016155A KR970004866A KR 970004866 A KR970004866 A KR 970004866A KR 1019950016155 A KR1019950016155 A KR 1019950016155A KR 19950016155 A KR19950016155 A KR 19950016155A KR 970004866 A KR970004866 A KR 970004866A
Authority
KR
South Korea
Prior art keywords
circuit
digital signal
signal delay
delay method
digital
Prior art date
Application number
KR1019950016155A
Other languages
English (en)
Other versions
KR0165404B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to KR1019950016155A priority Critical patent/KR0165404B1/ko
Priority to US08/663,772 priority patent/US5754071A/en
Priority to JP8155863A priority patent/JPH0923143A/ja
Publication of KR970004866A publication Critical patent/KR970004866A/ko
Application granted granted Critical
Publication of KR0165404B1 publication Critical patent/KR0165404B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Pulse Circuits (AREA)
KR1019950016155A 1995-06-17 1995-06-17 디지탈 신호의 지연방법 및 회로 KR0165404B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950016155A KR0165404B1 (ko) 1995-06-17 1995-06-17 디지탈 신호의 지연방법 및 회로
US08/663,772 US5754071A (en) 1995-06-17 1996-06-14 Digital signal delaying method and circuit
JP8155863A JPH0923143A (ja) 1995-06-17 1996-06-17 ディジタル信号の遅延方法及び回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950016155A KR0165404B1 (ko) 1995-06-17 1995-06-17 디지탈 신호의 지연방법 및 회로

Publications (2)

Publication Number Publication Date
KR970004866A true KR970004866A (ko) 1997-01-29
KR0165404B1 KR0165404B1 (ko) 1999-03-20

Family

ID=19417403

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950016155A KR0165404B1 (ko) 1995-06-17 1995-06-17 디지탈 신호의 지연방법 및 회로

Country Status (3)

Country Link
US (1) US5754071A (ko)
JP (1) JPH0923143A (ko)
KR (1) KR0165404B1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999062173A1 (en) * 1998-05-27 1999-12-02 Thomson Consumer Electronics, Inc. Synchronous reset generation in an asynchronous system
DE10200276A1 (de) * 2002-01-07 2003-07-17 Siemens Ag Eingangsschaltung und Verfahren zu deren Betrieb
US6882195B2 (en) * 2002-07-12 2005-04-19 Ics Technologies, Inc. Signal timing adjustment circuit with external resistor
KR100608355B1 (ko) * 2004-03-25 2006-08-08 주식회사 하이닉스반도체 메모리 장치의 동작 주파수 변동에 따른 내부 제어 신호의인에이블 구간을 제어하는 장치와 그 방법
US8125203B2 (en) * 2006-09-14 2012-02-28 Renesas Electronics Corporation PFC controller, switching regulator and power supply circuit
CN111600582B (zh) * 2020-06-04 2022-07-01 中国科学院合肥物质科学研究院 一种精密可调节的多路脉冲同步触发系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62281513A (ja) * 1986-05-29 1987-12-07 Fujitsu Ltd 遅延回路
US4795984A (en) * 1986-11-19 1989-01-03 Schlumberger Systems & Services, Inc. Multi-marker, multi-destination timing signal generator
JPS63133715A (ja) * 1986-11-25 1988-06-06 Mitsubishi Electric Corp 可変デイジタル遅延回路
JPH03213010A (ja) * 1990-01-18 1991-09-18 Sharp Corp クロック発生器
SE9300679L (sv) * 1993-03-01 1994-09-02 Ellemtel Utvecklings Ab Bitsynkroniserare
GB2287812B (en) * 1994-03-24 1997-09-24 Discovision Ass Clock divider

Also Published As

Publication number Publication date
US5754071A (en) 1998-05-19
KR0165404B1 (ko) 1999-03-20
JPH0923143A (ja) 1997-01-21

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