DE69630730D1 - Analogabtastpfadzelle - Google Patents

Analogabtastpfadzelle

Info

Publication number
DE69630730D1
DE69630730D1 DE69630730T DE69630730T DE69630730D1 DE 69630730 D1 DE69630730 D1 DE 69630730D1 DE 69630730 T DE69630730 T DE 69630730T DE 69630730 T DE69630730 T DE 69630730T DE 69630730 D1 DE69630730 D1 DE 69630730D1
Authority
DE
Germany
Prior art keywords
test voltage
signal path
analogabtastpfadzelle
voltage node
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69630730T
Other languages
English (en)
Other versions
DE69630730T2 (de
Inventor
Lee D Whetsel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69630730D1 publication Critical patent/DE69630730D1/de
Publication of DE69630730T2 publication Critical patent/DE69630730T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/3167—Testing of combined analog and digital circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69630730T 1995-05-31 1996-05-31 Analogabtastpfadzelle Expired - Lifetime DE69630730T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US45479595A 1995-05-31 1995-05-31
US454795 1995-05-31

Publications (2)

Publication Number Publication Date
DE69630730D1 true DE69630730D1 (de) 2003-12-24
DE69630730T2 DE69630730T2 (de) 2004-09-30

Family

ID=23806127

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69630730T Expired - Lifetime DE69630730T2 (de) 1995-05-31 1996-05-31 Analogabtastpfadzelle

Country Status (4)

Country Link
US (1) US5872908A (de)
EP (1) EP0745935B1 (de)
JP (1) JP3983318B2 (de)
DE (1) DE69630730T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US6260165B1 (en) 1996-10-18 2001-07-10 Texas Instruments Incorporated Accelerating scan test by re-using response data as stimulus data
US6125464A (en) * 1997-10-16 2000-09-26 Adaptec, Inc. High speed boundary scan design
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
DE19813503C1 (de) * 1998-03-26 2000-03-09 Siemens Ag Schaltungsanordnung zum Verhindern von bei Kontaktfehlern auftretenden falschen Ergebnissen beim Testen einer integrierten Schaltung
US6389566B1 (en) * 1998-06-02 2002-05-14 S3 Incorporated Edge-triggered scan flip-flop and one-pass scan synthesis methodology
US6163864A (en) * 1998-06-10 2000-12-19 Compaq Computer Corporation Method for cost-effective production testing of input voltage levels of the forwarded clock interface of high performance integrated circuits
US6560734B1 (en) 1998-06-19 2003-05-06 Texas Instruments Incorporated IC with addressable test port
US6519729B1 (en) 1998-06-27 2003-02-11 Texas Instruments Incorporated Reduced power testing with equally divided scan paths
US6185709B1 (en) * 1998-06-30 2001-02-06 International Business Machines Corporation Device for indicating the fixability of a logic circuit
US6266801B1 (en) * 1998-09-15 2001-07-24 Adaptec, Inc. Boundary-scan cells with improved timing characteristics
US7058862B2 (en) * 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
US6385748B1 (en) * 1999-03-30 2002-05-07 Nec Electronics, Inc. Direct access logic testing in integrated circuits
US6316933B1 (en) 1999-08-26 2001-11-13 Broadcom Corporation Test bus circuit and associated method
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US7032151B2 (en) * 2001-11-13 2006-04-18 Georgia Tech Research Corporation Systems and methods for testing integrated circuits
US6885213B2 (en) 2002-09-13 2005-04-26 Logicvision, Inc. Circuit and method for accurately applying a voltage to a node of an integrated circuit
AU2003290620A1 (en) * 2002-11-14 2004-06-03 Logicvision, Inc. Boundary scan with strobed pad driver enable
US7508228B2 (en) * 2004-12-21 2009-03-24 Teradyne, Inc. Method and system for monitoring test signals for semiconductor devices
JP5155146B2 (ja) * 2005-03-15 2013-02-27 サーモディクス，インコーポレイティド 挿入可能な医療器具用の柔軟性ポリマー被膜
ATE472106T1 (de) * 2005-10-24 2010-07-15 Nxp Bv Ic-testverfahren und vorrichtung
WO2009081743A1 (ja) * 2007-12-21 2009-07-02 Sony Corporation アナログスキャン回路、アナログフリップフロップおよびデータ処理装置
US8321730B2 (en) * 2009-12-29 2012-11-27 Intel Corporation Scan architecture and design methodology yielding significant reduction in scan area and power overhead
US8615694B2 (en) * 2011-02-07 2013-12-24 Texas Instruments Incorporated Interposer TAP boundary register coupling stacked die functional input/output data
CN113938125B (zh) * 2021-10-19 2023-02-24 浙江大学 多通道可配置可测试与修调的数字信号隔离器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047710A (en) * 1987-10-07 1991-09-10 Xilinx, Inc. System for scan testing of logic circuit networks
US5206545A (en) * 1991-02-05 1993-04-27 Vlsi Technology, Inc. Method and apparatus for providing output contention relief for digital buffers
US5323107A (en) * 1991-04-15 1994-06-21 Hitachi America, Ltd. Active probe card
US5297066A (en) * 1991-10-22 1994-03-22 National Semiconductor Corporation Digital circuit simulation of analog/digital circuits
US5285152A (en) * 1992-03-23 1994-02-08 Ministar Peripherals International Limited Apparatus and methods for testing circuit board interconnect integrity
US5404358A (en) * 1993-02-04 1995-04-04 Bull Hn Information Systems Inc. Boundary scan architecture analog extension
US5424659A (en) * 1994-06-20 1995-06-13 International Business Machines Corp. Mixed voltage output buffer circuit
CA2201623A1 (en) * 1994-10-06 1996-04-18 Stephen K. Sunter Bus for sensitive analog signals

Also Published As

Publication number Publication date
DE69630730T2 (de) 2004-09-30
EP0745935A1 (de) 1996-12-04
US5872908A (en) 1999-02-16
EP0745935B1 (de) 2003-11-19
JP3983318B2 (ja) 2007-09-26
JPH09218249A (ja) 1997-08-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition