DE69626654D1 - Mehrfaches schreiben pro einfachem löschen in nichtflüchtigem speicher - Google Patents

Mehrfaches schreiben pro einfachem löschen in nichtflüchtigem speicher

Info

Publication number
DE69626654D1
DE69626654D1 DE69626654T DE69626654T DE69626654D1 DE 69626654 D1 DE69626654 D1 DE 69626654D1 DE 69626654 T DE69626654 T DE 69626654T DE 69626654 T DE69626654 T DE 69626654T DE 69626654 D1 DE69626654 D1 DE 69626654D1
Authority
DE
Germany
Prior art keywords
volatile storage
multiple writing
writing per
simple erase
per simple
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69626654T
Other languages
English (en)
Other versions
DE69626654T2 (de
Inventor
N Hasbun
P Janecek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/537,132 external-priority patent/US5815434A/en
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69626654D1 publication Critical patent/DE69626654D1/de
Publication of DE69626654T2 publication Critical patent/DE69626654T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
DE69626654T 1995-09-29 1996-09-24 Mehrfaches schreiben pro einfachem löschen in nichtflüchtigem speicher Expired - Lifetime DE69626654T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US685939 1991-04-16
US537132 1995-09-29
US08/537,132 US5815434A (en) 1995-09-29 1995-09-29 Multiple writes per a single erase for a nonvolatile memory
US08/685,939 US5936884A (en) 1995-09-29 1996-07-22 Multiple writes per a single erase for a nonvolatile memory
PCT/US1996/015259 WO1997012368A1 (en) 1995-09-29 1996-09-24 Multiple writes per a single erase for a nonvolatile memory

Publications (2)

Publication Number Publication Date
DE69626654D1 true DE69626654D1 (de) 2003-04-17
DE69626654T2 DE69626654T2 (de) 2004-02-05

Family

ID=27065382

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69626654T Expired - Lifetime DE69626654T2 (de) 1995-09-29 1996-09-24 Mehrfaches schreiben pro einfachem löschen in nichtflüchtigem speicher

Country Status (8)

Country Link
EP (1) EP0852798B1 (de)
CN (1) CN1114214C (de)
AU (1) AU7165696A (de)
DE (1) DE69626654T2 (de)
HK (1) HK1015519A1 (de)
IL (1) IL123688A (de)
MX (1) MX9802298A (de)
WO (1) WO1997012368A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60134870D1 (de) 2001-12-28 2008-08-28 St Microelectronics Srl Programmierverfahren für eine Multibitspeicherzelle
US7132350B2 (en) 2003-07-21 2006-11-07 Macronix International Co., Ltd. Method for manufacturing a programmable eraseless memory
EP1503384A3 (de) * 2003-07-21 2007-07-18 Macronix International Co., Ltd. Verfahren zur Speicherprogrammierung
KR101303177B1 (ko) * 2007-06-22 2013-09-17 삼성전자주식회사 불휘발성 메모리 소자 및 그 동작 방법
KR101544607B1 (ko) 2008-10-28 2015-08-17 삼성전자주식회사 메모리 장치 및 그 프로그램 방법
US8149607B2 (en) * 2009-12-21 2012-04-03 Sandisk 3D Llc Rewritable memory device with multi-level, write-once memory cells
KR101438072B1 (ko) 2010-04-15 2014-09-03 라모트 앳 텔-아비브 유니버시티 리미티드 소거 없는 플래시 메모리의 다중 프로그래밍
US10261897B2 (en) 2017-01-20 2019-04-16 Samsung Electronics Co., Ltd. Tail latency aware foreground garbage collection algorithm

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5163021A (en) * 1989-04-13 1992-11-10 Sundisk Corporation Multi-state EEprom read and write circuits and techniques
US5487033A (en) * 1994-06-28 1996-01-23 Intel Corporation Structure and method for low current programming of flash EEPROMS

Also Published As

Publication number Publication date
DE69626654T2 (de) 2004-02-05
EP0852798A4 (de) 1999-05-26
EP0852798B1 (de) 2003-03-12
AU7165696A (en) 1997-04-17
HK1015519A1 (en) 1999-10-15
IL123688A (en) 2000-12-06
CN1202262A (zh) 1998-12-16
EP0852798A1 (de) 1998-07-15
MX9802298A (es) 1998-08-30
CN1114214C (zh) 2003-07-09
IL123688A0 (en) 1998-10-30
WO1997012368A1 (en) 1997-04-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition