DE69619468D1 - Ausgangstreiber für Systeme mit gemischtem Spannungsbetrieb - Google Patents

Ausgangstreiber für Systeme mit gemischtem Spannungsbetrieb

Info

Publication number
DE69619468D1
DE69619468D1 DE69619468T DE69619468T DE69619468D1 DE 69619468 D1 DE69619468 D1 DE 69619468D1 DE 69619468 T DE69619468 T DE 69619468T DE 69619468 T DE69619468 T DE 69619468T DE 69619468 D1 DE69619468 D1 DE 69619468D1
Authority
DE
Germany
Prior art keywords
systems
output driver
voltage operation
mixed voltage
mixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69619468T
Other languages
English (en)
Other versions
DE69619468T2 (de
Inventor
Ray Pinkham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix America Inc
Original Assignee
Hyundai Electronics America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics America Inc filed Critical Hyundai Electronics America Inc
Publication of DE69619468D1 publication Critical patent/DE69619468D1/de
Application granted granted Critical
Publication of DE69619468T2 publication Critical patent/DE69619468T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K17/063—Modifications for ensuring a fully conducting state in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
DE69619468T 1995-10-31 1996-10-30 Ausgangstreiber für Systeme mit gemischtem Spannungsbetrieb Expired - Lifetime DE69619468T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US55058695A 1995-10-31 1995-10-31

Publications (2)

Publication Number Publication Date
DE69619468D1 true DE69619468D1 (de) 2002-04-04
DE69619468T2 DE69619468T2 (de) 2003-05-08

Family

ID=24197786

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69619468T Expired - Lifetime DE69619468T2 (de) 1995-10-31 1996-10-30 Ausgangstreiber für Systeme mit gemischtem Spannungsbetrieb

Country Status (7)

Country Link
US (1) US5801569A (de)
EP (1) EP0772302B1 (de)
JP (1) JP3431774B2 (de)
KR (1) KR100263170B1 (de)
CN (1) CN1096712C (de)
DE (1) DE69619468T2 (de)
TW (1) TW333699B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100256247B1 (ko) * 1997-06-30 2000-05-15 김영환 포지티브 챠지 펌핑 장치
US5966036A (en) * 1997-09-09 1999-10-12 S3 Incorporated System and method for a mixed voltage drive system for floating substrate technology
US5917358A (en) * 1997-12-09 1999-06-29 Motorola, Inc. Method and output buffer with programmable bias to accommodate multiple supply voltages
JP3138680B2 (ja) * 1998-03-13 2001-02-26 日本電気アイシーマイコンシステム株式会社 出力バッファ制御回路
US5952866A (en) * 1998-04-28 1999-09-14 Lucent Technologies, Inc. CMOS output buffer protection circuit
JP3150127B2 (ja) * 1999-02-15 2001-03-26 日本電気株式会社 昇圧回路
GB9920172D0 (en) * 1999-08-25 1999-10-27 Sgs Thomson Microelectronics Cmos switching cicuitry
US6400189B2 (en) * 1999-12-14 2002-06-04 Intel Corporation Buffer circuit
US6313672B1 (en) * 1999-12-15 2001-11-06 Exar Corporation Over-voltage tolerant integrated circuit I/O buffer
US6313671B1 (en) * 1999-12-15 2001-11-06 Exar Corporation Low-power integrated circuit I/O buffer
US6353524B1 (en) 2000-03-17 2002-03-05 International Business Machines Corporation Input/output circuit having up-shifting circuitry for accommodating different voltage signals
US7253675B2 (en) * 2005-03-08 2007-08-07 Texas Instruments Incorporated Bootstrapping circuit capable of sampling inputs beyond supply voltage
US7771115B2 (en) * 2007-08-16 2010-08-10 Micron Technology, Inc. Temperature sensor circuit, device, system, and method
US20100321083A1 (en) * 2009-06-22 2010-12-23 International Business Machines Corporation Voltage Level Translating Circuit
US9378806B2 (en) * 2013-12-16 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Boosting voltage level
CN109741778A (zh) * 2018-12-29 2019-05-10 西安紫光国芯半导体有限公司 一种dram输出驱动电路及其减小漏电的方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656369A (en) * 1984-09-17 1987-04-07 Texas Instruments Incorporated Ring oscillator substrate bias generator with precharge voltage feedback control
US4667313A (en) * 1985-01-22 1987-05-19 Texas Instruments Incorporated Serially accessed semiconductor memory with tapped shift register
US4689495A (en) * 1985-06-17 1987-08-25 Advanced Micro Devices, Inc. CMOS high voltage switch
US4817058A (en) * 1987-05-21 1989-03-28 Texas Instruments Incorporated Multiple input/output read/write memory having a multiple-cycle write mask
FR2642240B1 (fr) * 1989-01-23 1994-07-29 Sgs Thomson Microelectronics Circuit a transistor mos de puissance commande par un dispositif a deux pompes de charge symetriques
KR930003929B1 (ko) * 1990-08-09 1993-05-15 삼성전자 주식회사 데이타 출력버퍼
US5128560A (en) * 1991-03-22 1992-07-07 Micron Technology, Inc. Boosted supply output driver circuit for driving an all N-channel output stage
US5321324A (en) * 1993-01-28 1994-06-14 United Memories, Inc. Low-to-high voltage translator with latch-up immunity
US5399920A (en) * 1993-11-09 1995-03-21 Texas Instruments Incorporated CMOS driver which uses a higher voltage to compensate for threshold loss of the pull-up NFET
KR0120565B1 (ko) * 1994-04-18 1997-10-30 김주용 래치-업을 방지한 씨모스형 데이타 출력버퍼

Also Published As

Publication number Publication date
CN1162846A (zh) 1997-10-22
JP3431774B2 (ja) 2003-07-28
CN1096712C (zh) 2002-12-18
EP0772302A2 (de) 1997-05-07
TW333699B (en) 1998-06-11
KR970023433A (ko) 1997-05-30
EP0772302B1 (de) 2002-02-27
JPH09167958A (ja) 1997-06-24
US5801569A (en) 1998-09-01
KR100263170B1 (ko) 2000-08-01
EP0772302A3 (de) 1999-03-10
DE69619468T2 (de) 2003-05-08

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication related to discontinuation of the patent is to be deleted
8364 No opposition during term of opposition