DE69533620D1 - Zweistufige taktfilterschaltung zur regenerierung eines e4 nachrichtensignals aus der datenkomponente eines sts-3c signals - Google Patents

Zweistufige taktfilterschaltung zur regenerierung eines e4 nachrichtensignals aus der datenkomponente eines sts-3c signals

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Publication number
DE69533620D1
DE69533620D1 DE69533620T DE69533620T DE69533620D1 DE 69533620 D1 DE69533620 D1 DE 69533620D1 DE 69533620 T DE69533620 T DE 69533620T DE 69533620 T DE69533620 T DE 69533620T DE 69533620 D1 DE69533620 D1 DE 69533620D1
Authority
DE
Germany
Prior art keywords
signal
sts
regenerating
filter circuit
data component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69533620T
Other languages
English (en)
Other versions
DE69533620T2 (de
Inventor
C Upp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Transwitch Corp
Original Assignee
Transwitch Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Transwitch Corp filed Critical Transwitch Corp
Publication of DE69533620D1 publication Critical patent/DE69533620D1/de
Application granted granted Critical
Publication of DE69533620T2 publication Critical patent/DE69533620T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/07Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/061Adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or average clock frequency, at the other side; Not pulse stuffing only
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/126Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE69533620T 1994-07-08 1995-06-30 Zweistufige taktfilterschaltung zur regenerierung eines e4 nachrichtensignals aus der datenkomponente eines sts-3c signals Expired - Lifetime DE69533620T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US272259 1994-07-08
US08/272,259 US5548534A (en) 1994-07-08 1994-07-08 Two stage clock dejitter circuit for regenerating an E4 telecommunications signal from the data component of an STS-3C signal
PCT/US1995/008260 WO1996002095A1 (en) 1994-07-08 1995-06-30 Two stage clock dejitter circuit for regenerating an e4 telecommunications signal from the data component of an sts-3c signal

Publications (2)

Publication Number Publication Date
DE69533620D1 true DE69533620D1 (de) 2004-11-11
DE69533620T2 DE69533620T2 (de) 2006-02-09

Family

ID=23039071

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69533620T Expired - Lifetime DE69533620T2 (de) 1994-07-08 1995-06-30 Zweistufige taktfilterschaltung zur regenerierung eines e4 nachrichtensignals aus der datenkomponente eines sts-3c signals

Country Status (5)

Country Link
US (1) US5548534A (de)
EP (1) EP0770292B1 (de)
CA (1) CA2192161C (de)
DE (1) DE69533620T2 (de)
WO (1) WO1996002095A1 (de)

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US6512804B1 (en) 1999-04-07 2003-01-28 Applied Micro Circuits Corporation Apparatus and method for multiple serial data synchronization using channel-lock FIFO buffers optimized for jitter
US6721336B1 (en) 1999-12-22 2004-04-13 Alcatel STS-n with enhanced granularity
US6577651B2 (en) * 2001-01-24 2003-06-10 Transwitch Corp. Methods and apparatus for retiming and realigning sonet signals
US6836854B2 (en) * 2001-04-03 2004-12-28 Applied Micro Circuits Corporation DS3 Desynchronizer with a module for providing uniformly gapped data signal to a PLL module for providing a smooth output data signal
US6463111B1 (en) * 2001-05-25 2002-10-08 Transwitch Corporaton Method and apparatus for desynchronizing a DS-3 signal and/or an E3 signal from the data portion of an STS-STM payload
US6882662B2 (en) * 2001-06-07 2005-04-19 Applied Micro Circuits Corporation Pointer adjustment wander and jitter reduction apparatus for a desynchronizer
US7212599B2 (en) * 2002-01-25 2007-05-01 Applied Micro Circuits Corporation Jitter and wander reduction apparatus
US7227876B1 (en) * 2002-01-28 2007-06-05 Pmc-Sierra, Inc. FIFO buffer depth estimation for asynchronous gapped payloads
US7180914B2 (en) * 2002-08-19 2007-02-20 Applied Micro Circuits Corporation Efficient asynchronous stuffing insertion and destuffing removal circuit
AU2002349257A1 (en) * 2002-11-06 2004-06-07 Wuhan Fiberhome Networks Co., Ltd. Multiple service ring of n-ringlet structure based on multiple fe, ge and 10ge
US20040156463A1 (en) * 2003-02-11 2004-08-12 Goodloe Anthony A. System and method for recovering a payload data stream from a framing data stream
US8588354B2 (en) * 2006-02-09 2013-11-19 Flextronics Ap, Llc Egress pointer smoother
US7630397B2 (en) * 2006-10-26 2009-12-08 Transwitch Corporation Efficient scalable implementation of VCAT/LCAS for SDH and PDH signals

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Also Published As

Publication number Publication date
CA2192161A1 (en) 1996-01-25
CA2192161C (en) 2004-06-22
EP0770292A1 (de) 1997-05-02
EP0770292A4 (de) 1999-04-21
DE69533620T2 (de) 2006-02-09
US5548534A (en) 1996-08-20
EP0770292B1 (de) 2004-10-06
WO1996002095A1 (en) 1996-01-25

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