DE69528914T2 - Verbindungsprüfung unter Verwendung von Leiterplatten-Topologiedaten - Google Patents

Verbindungsprüfung unter Verwendung von Leiterplatten-Topologiedaten

Info

Publication number
DE69528914T2
DE69528914T2 DE69528914T DE69528914T DE69528914T2 DE 69528914 T2 DE69528914 T2 DE 69528914T2 DE 69528914 T DE69528914 T DE 69528914T DE 69528914 T DE69528914 T DE 69528914T DE 69528914 T2 DE69528914 T2 DE 69528914T2
Authority
DE
Germany
Prior art keywords
circuit board
topology data
connection check
enhanced
diagnosis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69528914T
Other languages
English (en)
Other versions
DE69528914D1 (de
Inventor
Kenneth P Parker
Kenneth E Posse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of DE69528914D1 publication Critical patent/DE69528914D1/de
Application granted granted Critical
Publication of DE69528914T2 publication Critical patent/DE69528914T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318561—Identification of the subpart
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G01R31/318538—Topological or mechanical aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318566—Comparators; Diagnosing the device under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
DE69528914T 1994-03-09 1995-02-17 Verbindungsprüfung unter Verwendung von Leiterplatten-Topologiedaten Expired - Fee Related DE69528914T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/208,245 US5513188A (en) 1991-09-10 1994-03-09 Enhanced interconnect testing through utilization of board topology data

Publications (2)

Publication Number Publication Date
DE69528914D1 DE69528914D1 (de) 2003-01-02
DE69528914T2 true DE69528914T2 (de) 2003-07-31

Family

ID=22773854

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69528914T Expired - Fee Related DE69528914T2 (de) 1994-03-09 1995-02-17 Verbindungsprüfung unter Verwendung von Leiterplatten-Topologiedaten

Country Status (4)

Country Link
US (1) US5513188A (de)
EP (2) EP0671689A3 (de)
JP (1) JP3686445B2 (de)
DE (1) DE69528914T2 (de)

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JPH07175851A (ja) * 1993-10-28 1995-07-14 Mitsubishi Electric Corp バスチェック装置及びバスチェック方法
US5606565A (en) * 1995-02-14 1997-02-25 Hughes Electronics Method of applying boundary test patterns
EP0758771B1 (de) * 1995-08-10 1998-06-03 Hewlett-Packard GmbH Elektronischer Schaltungs- oder Kartenprüfer und Verfahren zur Prüfung einer elektronischen Vorrichtung
JP3249040B2 (ja) * 1995-12-05 2002-01-21 株式会社アドバンテスト スキャンテスト装置
US5740086A (en) * 1996-01-11 1998-04-14 Advantest Corp. Semiconductor test system linked to cad data
US5661733A (en) * 1996-04-10 1997-08-26 Hughes Electronics Automatic test insertion
US5898705A (en) * 1996-12-23 1999-04-27 Lsi Logic Corporation Method for detecting bus shorts in semiconductor devices
US6477486B1 (en) * 1998-09-10 2002-11-05 Dell Usa, L.P. Automatic location determination of devices under test
US6467051B1 (en) * 1998-10-09 2002-10-15 Agilent Technologies, Inc. Method and apparatus for selecting test point nodes of a group of components having both accessible and inaccessible nodes for limited access circuit test
US6378094B1 (en) * 1999-04-01 2002-04-23 Lucent Technologies Inc. Method and system for testing cluster circuits in a boundary scan environment
JP2000304829A (ja) 1999-04-21 2000-11-02 Matsushita Electric Ind Co Ltd 半導体検査方法
US6785846B2 (en) * 2000-12-22 2004-08-31 Intel Corporation Inexpensive method for diagnosing manufacturing defects in an embedded system
JP2002311090A (ja) * 2001-04-09 2002-10-23 Mitsubishi Electric Corp 半導体集積回路およびテスト用ボード
US7174492B1 (en) 2001-04-12 2007-02-06 Cisco Technology, Inc. AC coupled line testing using boundary scan test methodology
DE10226876B4 (de) * 2002-06-12 2008-07-10 Dr. Johannes Heidenhain Gmbh Vorrichtung und Verfahren zur Überprüfung eines Bussystems
US6862705B1 (en) * 2002-08-21 2005-03-01 Applied Micro Circuits Corporation System and method for testing high pin count electronic devices using a test board with test channels
AU2003290620A1 (en) 2002-11-14 2004-06-03 Logicvision, Inc. Boundary scan with strobed pad driver enable
JP2004264057A (ja) * 2003-02-12 2004-09-24 Sharp Corp バウンダリスキャンコントローラ、半導体装置、半導体装置の半導体回路チップ識別方法、半導体装置の半導体回路チップ制御方法
US7240265B1 (en) * 2003-04-28 2007-07-03 Corelis, Inc. Apparatus for use in detecting circuit faults during boundary scan testing
US6940299B1 (en) * 2004-05-04 2005-09-06 National Semiconductor Corporation Method of testing for short circuits between adjacent input/output pins of an integrated circuit
GB0419868D0 (en) * 2004-09-08 2004-10-13 Koninkl Philips Electronics Nv Testing of a system-on-chip integrated circuit
US7596736B2 (en) * 2006-03-24 2009-09-29 International Business Machines Corporation Iterative process for identifying systematics in data
KR20090097855A (ko) 2007-01-17 2009-09-16 인터내셔널 비지네스 머신즈 코포레이션 추가적인 장치와 연결되거나 또는 연결될 수 있는 전기 장치의 전류 회귀 경로 무결성을 판정하기 위한 방법
US7853848B2 (en) * 2007-10-22 2010-12-14 International Business Machines Corporation System and method for signature-based systematic condition detection and analysis
US7821281B2 (en) * 2009-02-23 2010-10-26 Faraday Technology Corp. Method and apparatus of testing die to die interconnection for system in package
CN102279357B (zh) * 2011-06-23 2013-11-06 哈尔滨工业大学 一种基于边界扫描技术的分解式电路互连测试方法
CN102495358B (zh) * 2011-12-01 2013-09-18 北京航天测控技术有限公司 一种考虑约束条件的边界扫描测试方法
US9103867B2 (en) * 2012-08-09 2015-08-11 Shenzhen China Star Optoelectronics Technology Co., Ltd Apparatus and method for detecting the abnormal soldering of an electrostatic discharge protection chip
US9791505B1 (en) * 2016-04-29 2017-10-17 Texas Instruments Incorporated Full pad coverage boundary scan

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0246034A3 (de) * 1986-05-16 1989-04-05 AT&T Corp. Prüfung elektronischer Schaltungen während ihrer Herstellung
US5027353A (en) * 1989-04-17 1991-06-25 At&T Bell Laboratories Method for testing interconnections
US5029166A (en) * 1989-05-31 1991-07-02 At&T Bell Laboratories Method and apparatus for testing circuit boards
US5172377A (en) * 1990-09-07 1992-12-15 Genrad, Inc. Method for testing mixed scan and non-scan circuitry
US5130988A (en) * 1990-09-17 1992-07-14 Northern Telecom Limited Software verification by fault insertion
US5166937A (en) * 1990-12-26 1992-11-24 Ag Communication System Corporation Arrangement for testing digital circuit devices having tri-state outputs
EP0543506B1 (de) * 1991-11-19 1997-03-05 Hewlett-Packard Company Verbesserte Diagnose der Verbindungsprüfung mittels "boundary-scan"-Technik durch Ausnutzung von Leiterplatten-Datentopologie
US5260649A (en) * 1992-01-03 1993-11-09 Hewlett-Packard Company Powered testing of mixed conventional/boundary-scan logic
IT1259395B (it) * 1992-05-29 1996-03-13 Luciano Bonaria Metodo di rilevamento di connesioni erronee in schede elettroniche

Also Published As

Publication number Publication date
EP0930570B1 (de) 2002-11-20
EP0930570A3 (de) 1999-07-28
EP0671689A3 (de) 1995-12-27
US5513188A (en) 1996-04-30
DE69528914D1 (de) 2003-01-02
JP3686445B2 (ja) 2005-08-24
JPH07280887A (ja) 1995-10-27
EP0930570A2 (de) 1999-07-21
EP0671689A2 (de) 1995-09-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US

8339 Ceased/non-payment of the annual fee