DE69516769T2 - Planarisierter isolationsgraben und feldoxid-isolationsstruktur - Google Patents

Planarisierter isolationsgraben und feldoxid-isolationsstruktur

Info

Publication number
DE69516769T2
DE69516769T2 DE69516769T DE69516769T DE69516769T2 DE 69516769 T2 DE69516769 T2 DE 69516769T2 DE 69516769 T DE69516769 T DE 69516769T DE 69516769 T DE69516769 T DE 69516769T DE 69516769 T2 DE69516769 T2 DE 69516769T2
Authority
DE
Germany
Prior art keywords
insulation
field oxide
planarized
trench
insulation structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69516769T
Other languages
English (en)
Other versions
DE69516769D1 (de
Inventor
Rashid Bashir
Francois Hebert
Datong Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of DE69516769D1 publication Critical patent/DE69516769D1/de
Application granted granted Critical
Publication of DE69516769T2 publication Critical patent/DE69516769T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material
DE69516769T 1994-03-15 1995-02-27 Planarisierter isolationsgraben und feldoxid-isolationsstruktur Expired - Lifetime DE69516769T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US21296794A 1994-03-15 1994-03-15
PCT/US1995/002498 WO1995025343A1 (en) 1994-03-15 1995-02-27 Planarized trench and field oxide isolation scheme

Publications (2)

Publication Number Publication Date
DE69516769D1 DE69516769D1 (de) 2000-06-15
DE69516769T2 true DE69516769T2 (de) 2000-12-28

Family

ID=22793159

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69516769T Expired - Lifetime DE69516769T2 (de) 1994-03-15 1995-02-27 Planarisierter isolationsgraben und feldoxid-isolationsstruktur

Country Status (5)

Country Link
US (2) US5683932A (de)
EP (1) EP0698284B1 (de)
KR (1) KR100329061B1 (de)
DE (1) DE69516769T2 (de)
WO (1) WO1995025343A1 (de)

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US5943578A (en) * 1993-02-05 1999-08-24 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device having an element isolating region
US6307273B1 (en) * 1996-06-07 2001-10-23 Vanguard International Semiconductor Corporation High contrast, low noise alignment mark for laser trimming of redundant memory arrays
US6322634B1 (en) * 1997-01-27 2001-11-27 Micron Technology, Inc. Shallow trench isolation structure without corner exposure
SE512813C2 (sv) * 1997-05-23 2000-05-15 Ericsson Telefon Ab L M Förfarande för framställning av en integrerad krets innefattande en dislokationsfri kollektorplugg förbunden med en begravd kollektor i en halvledarkomponent, som är omgiven av en dislokationsfri trench samt integrerad krets framställd enligt förfarandet
TW359005B (en) * 1997-09-01 1999-05-21 United Microelectronics Corp Method for manufacturing mixed circuit bi-gap wall structure
TW365049B (en) * 1997-10-18 1999-07-21 United Microelectronics Corp Manufacturing method for shallow trench isolation structure
DE19751740B4 (de) * 1997-11-21 2005-03-10 Infineon Technologies Ag Verfahren zur Herstellung einer integrierten Schaltung mit unterschiedlich tiefen Isolationsgräben
KR19990058297A (ko) * 1997-12-30 1999-07-15 김규현 반도체 소자 분리를 위한 트랜치 구조 및 그 형성방법
KR100253406B1 (ko) 1998-01-20 2000-04-15 김영환 반도체 파워 집적회로에서의 소자격리구조 및 그 방법
US6440819B1 (en) * 1998-03-03 2002-08-27 Advanced Micro Devices, Inc. Method for differential trenching in conjunction with differential fieldox growth
KR100275730B1 (ko) * 1998-05-11 2000-12-15 윤종용 트렌치 소자분리 방법
KR100468712B1 (ko) * 1998-06-19 2005-04-06 삼성전자주식회사 열산화 공정을 포함하지 않는 반도체장치의 트렌치 소자분리방법
TW395024B (en) * 1998-08-28 2000-06-21 United Microelectronics Corp The method to shape up a shallow trench for isolation in IC
US6601761B1 (en) 1998-09-15 2003-08-05 Citibank, N.A. Method and system for co-branding an electronic payment platform such as an electronic wallet
US6239002B1 (en) * 1998-10-19 2001-05-29 Taiwan Semiconductor Manufacturing Company Thermal oxidizing method for forming with attenuated surface sensitivity ozone-teos silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer
US6060348A (en) * 1998-11-02 2000-05-09 Vanguard International Semiconducter Corporation Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technology
US7045435B1 (en) * 1998-11-03 2006-05-16 Mosel Vitelic Inc Shallow trench isolation method for a semiconductor wafer
KR20000040104A (ko) * 1998-12-17 2000-07-05 김영환 실리콘 온 인슐레이터 웨이퍼의 제조방법
US6245639B1 (en) * 1999-02-08 2001-06-12 Taiwan Semiconductor Manufacturing Company Method to reduce a reverse narrow channel effect for MOSFET devices
KR100338766B1 (ko) * 1999-05-20 2002-05-30 윤종용 티(ｔ)형 소자분리막 형성방법을 이용한 엘리베이티드 샐리사이드 소오스/드레인 영역 형성방법 및 이를 이용한 반도체 소자
US6372600B1 (en) * 1999-08-30 2002-04-16 Agere Systems Guardian Corp. Etch stops and alignment marks for bonded wafers
WO2001020664A1 (en) 1999-09-17 2001-03-22 Telefonaktiebolaget Lm Ericsson A self-aligned method for forming deep trenches in shallow trenches for isolation of semiconductor devices
US6229187B1 (en) 1999-10-20 2001-05-08 Advanced Micro Devices, Inc. Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer
US6245636B1 (en) 1999-10-20 2001-06-12 Advanced Micro Devices, Inc. Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate
US6376286B1 (en) * 1999-10-20 2002-04-23 Advanced Micro Devices, Inc. Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer
US6465852B1 (en) 1999-10-20 2002-10-15 Advanced Micro Devices, Inc. Silicon wafer including both bulk and SOI regions and method for forming same on a bulk silicon wafer
US6110797A (en) * 1999-12-06 2000-08-29 National Semiconductor Corporation Process for fabricating trench isolation structure for integrated circuits
KR100389031B1 (ko) * 2001-06-19 2003-06-25 삼성전자주식회사 트렌치 소자분리 구조를 가지는 반도체 소자의 제조방법
DE10142595C2 (de) * 2001-08-31 2003-10-09 Infineon Technologies Ag Verfahren zum Ausgleichen von unterschiedlichen Stufenhöhen und zum Herstellen von planaren Oxidschichten in einer integrierten Halbleiterschaltungsanordung
US6818528B2 (en) * 2001-10-24 2004-11-16 International Business Machines Corporation Method for multi-depth trench isolation
US6930027B2 (en) * 2003-02-18 2005-08-16 Freescale Semiconductor, Inc. Method of manufacturing a semiconductor component
US20050136588A1 (en) * 2003-12-23 2005-06-23 Chris Speyer Method of forming isolation regions
US7141478B2 (en) * 2004-01-26 2006-11-28 Legerity Inc. Multi-stage EPI process for forming semiconductor devices, and resulting device
JP2005276931A (ja) * 2004-03-23 2005-10-06 Toshiba Corp 半導体装置およびその製造方法
US20070054464A1 (en) * 2005-09-08 2007-03-08 Chartered Semiconductor Manufacturing Ltd. Different STI depth for Ron improvement for LDMOS integration with submicron devices
US8501632B2 (en) * 2005-12-20 2013-08-06 Infineon Technologies Ag Methods of fabricating isolation regions of semiconductor devices and structures thereof
US8936995B2 (en) * 2006-03-01 2015-01-20 Infineon Technologies Ag Methods of fabricating isolation regions of semiconductor devices and structures thereof
KR102209097B1 (ko) 2014-02-27 2021-01-28 삼성전자주식회사 이미지 센서 및 이의 제조 방법

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JPS57204133A (en) * 1981-06-10 1982-12-14 Hitachi Ltd Manufacture of semiconductor integrated circuit
US4472240A (en) * 1981-08-21 1984-09-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
JPS59177940A (ja) * 1983-03-28 1984-10-08 Nec Corp 素子分離領域の製造方法
JPS6367747A (ja) * 1986-09-09 1988-03-26 Sharp Corp 半導体装置の素子分離方法
DE69004932T2 (de) * 1989-10-25 1994-05-19 Ibm Verfahren zur Herstellung breiter mit Dielektrikum gefüllter Isolationsgraben für Halbleiteranordnungen.
US5385861A (en) * 1994-03-15 1995-01-31 National Semiconductor Corporation Planarized trench and field oxide and poly isolation scheme
US5411913A (en) * 1994-04-29 1995-05-02 National Semiconductor Corporation Simple planarized trench isolation and field oxide formation using poly-silicon

Also Published As

Publication number Publication date
EP0698284A1 (de) 1996-02-28
KR100329061B1 (ko) 2002-11-13
US5683932A (en) 1997-11-04
DE69516769D1 (de) 2000-06-15
KR960702677A (ko) 1996-04-27
EP0698284B1 (de) 2000-05-10
WO1995025343A1 (en) 1995-09-21
US5691232A (en) 1997-11-25

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