DE69513516D1 - Einchipsteuerungsspeicherandordnung und eine speicherarchitektur und verfahren zur inbetriebnahme derselben - Google Patents

Einchipsteuerungsspeicherandordnung und eine speicherarchitektur und verfahren zur inbetriebnahme derselben

Info

Publication number
DE69513516D1
DE69513516D1 DE69513516T DE69513516T DE69513516D1 DE 69513516 D1 DE69513516 D1 DE 69513516D1 DE 69513516 T DE69513516 T DE 69513516T DE 69513516 T DE69513516 T DE 69513516T DE 69513516 D1 DE69513516 D1 DE 69513516D1
Authority
DE
Germany
Prior art keywords
commissioning
chip control
storage
architecture
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69513516T
Other languages
English (en)
Other versions
DE69513516T2 (de
Inventor
G R Mohan Rao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic Inc
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22902907&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69513516(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Application granted granted Critical
Publication of DE69513516D1 publication Critical patent/DE69513516D1/de
Publication of DE69513516T2 publication Critical patent/DE69513516T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/81—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a hierarchical redundancy scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
DE69513516T 1994-05-09 1995-05-08 Einchipsteuerungsspeicherandordnung und eine speicherarchitektur und verfahren zur inbetriebnahme derselben Expired - Fee Related DE69513516T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/239,608 US5473573A (en) 1994-05-09 1994-05-09 Single chip controller-memory device and a memory architecture and methods suitable for implementing the same
PCT/US1995/005761 WO1995030988A1 (en) 1994-05-09 1995-05-08 A single chip controller-memory device and a memory architecture and methods suitable for implementing the same

Publications (2)

Publication Number Publication Date
DE69513516D1 true DE69513516D1 (de) 1999-12-30
DE69513516T2 DE69513516T2 (de) 2000-07-06

Family

ID=22902907

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69513516T Expired - Fee Related DE69513516T2 (de) 1994-05-09 1995-05-08 Einchipsteuerungsspeicherandordnung und eine speicherarchitektur und verfahren zur inbetriebnahme derselben
DE69528851T Expired - Fee Related DE69528851T2 (de) 1994-05-09 1995-05-08 Einchipsteuerungsspeicheranordnung und eine Speicherarchitektur und Verfahren zur Inbetriebnahme derselben

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69528851T Expired - Fee Related DE69528851T2 (de) 1994-05-09 1995-05-08 Einchipsteuerungsspeicheranordnung und eine Speicherarchitektur und Verfahren zur Inbetriebnahme derselben

Country Status (7)

Country Link
US (2) US5473573A (de)
EP (2) EP0760155B1 (de)
JP (1) JPH09508735A (de)
KR (1) KR100245310B1 (de)
DE (2) DE69513516T2 (de)
HK (1) HK1010011A1 (de)
WO (1) WO1995030988A1 (de)

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US5598525A (en) 1995-01-23 1997-01-28 Cirrus Logic, Inc. Apparatus, systems and methods for controlling graphics and video data in multimedia data processing and display systems
US5699315A (en) * 1995-03-24 1997-12-16 Texas Instruments Incorporated Data processing with energy-efficient, multi-divided module memory architectures
US6025840A (en) * 1995-09-27 2000-02-15 Cirrus Logic, Inc. Circuits, systems and methods for memory mapping and display control systems using the same
US5914906A (en) * 1995-12-20 1999-06-22 International Business Machines Corporation Field programmable memory array
US5671185A (en) * 1996-03-12 1997-09-23 United Microelectronics Corporation Apparatus for replacing defective cells in a memory device
US5982696A (en) * 1996-06-06 1999-11-09 Cirrus Logic, Inc. Memories with programmable address decoding and systems and methods using the same
US5870409A (en) * 1996-06-28 1999-02-09 Microchip Technology Incorporated Method and apparatus for testing a relatively slow speed component of an intergrated circuit having mixed slow speed and high speed components
US5781200A (en) * 1996-08-08 1998-07-14 Ulsi Systems Tile memory mapping for increased throughput in a dual bank access DRAM
US6230235B1 (en) 1996-08-08 2001-05-08 Apache Systems, Inc. Address lookup DRAM aging
US6104658A (en) * 1996-08-08 2000-08-15 Neomagic Corporation Distributed DRAM refreshing
US5877780A (en) * 1996-08-08 1999-03-02 Lu; Hsuehchung Shelton Semiconductor chip having multiple independent memory sections, at least one of which includes simultaneously accessible arrays
US6023745A (en) * 1996-08-08 2000-02-08 Neomagic Corporation Scoreboarding for DRAM access within a multi-array DRAM device using simultaneous activate and read/write accesses
US6000048A (en) * 1996-08-14 1999-12-07 Cirrus Logic, Inc. Combined logic and memory circuit with built-in memory test
US6857099B1 (en) * 1996-09-18 2005-02-15 Nippon Steel Corporation Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
US5901298A (en) * 1996-10-07 1999-05-04 Intel Corporation Method for utilizing a single multiplex address bus between DRAM, SRAM and ROM
US6208567B1 (en) 1997-01-31 2001-03-27 Matsushita Electric Industrial Co., Ltd. Semiconductor device capable of cutting off a leakage current in a defective array section
US5900887A (en) * 1997-05-05 1999-05-04 Neomagic Corp. Multiplexed wide interface to SGRAM on a graphics controller for complex-pattern fills without color and mask registers
US6157984A (en) * 1997-05-15 2000-12-05 Seagate Technology, Llc Integrated controller/processor for disc drive having direct memory access
US5953738A (en) * 1997-07-02 1999-09-14 Silicon Aquarius, Inc DRAM with integral SRAM and arithmetic-logic units
US6067255A (en) * 1997-07-03 2000-05-23 Samsung Electronics Co., Ltd. Merged memory and logic (MML) integrated circuits including independent memory bank signals and methods
US6154851A (en) * 1997-08-05 2000-11-28 Micron Technology, Inc. Memory repair
US6076947A (en) * 1997-08-29 2000-06-20 Lear Donnelly Overhead Systems, Llc Visor with illuminated vanity assembly
JP3833366B2 (ja) * 1997-10-31 2006-10-11 株式会社ルネサステクノロジ 画像データ記憶装置
US6484065B1 (en) 1997-12-29 2002-11-19 Kawasaki Microelectronics, Inc. DRAM enhanced processor
US6397299B1 (en) 1998-01-21 2002-05-28 Micron Technology, Inc. Reduced latency memory configuration method using non-cacheable memory physically distinct from main memory
US6560680B2 (en) 1998-01-21 2003-05-06 Micron Technology, Inc. System controller with Integrated low latency memory using non-cacheable memory physically distinct from main memory
US6104418A (en) * 1998-04-06 2000-08-15 Silicon Magic Corporation Method and system for improved memory interface during image rendering
US6240525B1 (en) * 1998-11-17 2001-05-29 Oak Technology, Inc. Method and apparatus for re-addressing defective memory cells
JP2000251035A (ja) * 1999-02-26 2000-09-14 Hitachi Ltd メモリカード
ATE229677T1 (de) * 1999-06-04 2002-12-15 Udekem D Acoz Xavier Guy Ber D Speicherkarte
US6795367B1 (en) * 2000-05-16 2004-09-21 Micron Technology, Inc. Layout technique for address signal lines in decoders including stitched blocks
JP3923715B2 (ja) * 2000-09-29 2007-06-06 株式会社東芝 メモリカード
JP2006507535A (ja) * 2002-11-22 2006-03-02 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチメディア・プレゼンテーションの装置および方法
US7347570B2 (en) * 2002-11-22 2008-03-25 International Business Machines Corporation Multimedia presentation apparatus and method
US7466100B2 (en) 2004-01-21 2008-12-16 Peaktronics, Inc. Digital high-resolution controller
KR100610006B1 (ko) * 2004-05-04 2006-08-08 삼성전자주식회사 호스트 시스템의 다중동작 지원에 적합한 메모리 구조를갖는 반도체 메모리 장치
JP2005340227A (ja) * 2004-05-24 2005-12-08 Hitachi Ltd 半導体記憶装置と半導体装置
US7957204B1 (en) * 2005-09-20 2011-06-07 Spansion Llc Flash memory programming power reduction
US7590015B2 (en) * 2006-08-30 2009-09-15 Seiko Epson Corporation Integrated circuit device and electronic instrument
US20080238928A1 (en) * 2007-03-30 2008-10-02 Bimal Poddar Frame buffer compression for desktop composition
US20130117615A1 (en) * 2011-11-07 2013-05-09 Su-a Kim Semiconductor memory device and system having redundancy cells

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Also Published As

Publication number Publication date
DE69513516T2 (de) 2000-07-06
EP0760155B1 (de) 1999-11-24
EP0895246B1 (de) 2001-11-21
DE69528851D1 (de) 2002-12-19
HK1010011A1 (en) 1999-06-11
DE69528851T2 (de) 2004-07-22
EP0760155A1 (de) 1997-03-05
WO1995030988A1 (en) 1995-11-16
KR970703596A (ko) 1997-07-03
JPH09508735A (ja) 1997-09-02
US5473573A (en) 1995-12-05
KR100245310B1 (ko) 2000-02-15
US5583822A (en) 1996-12-10
EP0895246A1 (de) 1999-02-03

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee