DE69737757D1 - System und Verfahren zur Speicher-Emulation - Google Patents

System und Verfahren zur Speicher-Emulation

Info

Publication number
DE69737757D1
DE69737757D1 DE69737757T DE69737757T DE69737757D1 DE 69737757 D1 DE69737757 D1 DE 69737757D1 DE 69737757 T DE69737757 T DE 69737757T DE 69737757 T DE69737757 T DE 69737757T DE 69737757 D1 DE69737757 D1 DE 69737757D1
Authority
DE
Germany
Prior art keywords
memory emulation
emulation
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69737757T
Other languages
English (en)
Other versions
DE69737757T2 (de
Inventor
John E Chilton
Tony R Sarno
Ingo Schaefer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quickturn Design Systems Inc
Original Assignee
Quickturn Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quickturn Design Systems Inc filed Critical Quickturn Design Systems Inc
Application granted granted Critical
Publication of DE69737757D1 publication Critical patent/DE69737757D1/de
Publication of DE69737757T2 publication Critical patent/DE69737757T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69737757T 1996-02-06 1997-02-05 System und Verfahren zur Speicher-Emulation Expired - Lifetime DE69737757T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US597197 1990-10-09
US08/597,197 US5819065A (en) 1995-06-28 1996-02-06 System and method for emulating memory

Publications (2)

Publication Number Publication Date
DE69737757D1 true DE69737757D1 (de) 2007-07-12
DE69737757T2 DE69737757T2 (de) 2008-01-31

Family

ID=24390505

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69737757T Expired - Lifetime DE69737757T2 (de) 1996-02-06 1997-02-05 System und Verfahren zur Speicher-Emulation

Country Status (4)

Country Link
US (1) US5819065A (de)
EP (1) EP0789311B1 (de)
JP (1) JP3995751B2 (de)
DE (1) DE69737757T2 (de)

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US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
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US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
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Also Published As

Publication number Publication date
DE69737757T2 (de) 2008-01-31
JP3995751B2 (ja) 2007-10-24
EP0789311A2 (de) 1997-08-13
EP0789311A3 (de) 2001-03-28
US5819065A (en) 1998-10-06
JPH1055288A (ja) 1998-02-24
EP0789311B1 (de) 2007-05-30

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Legal Events

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