DE69510866T2 - Lokaloxidierung von Silizium mit Isolierungsverfahren durch maskierte Seitenflächen - Google Patents

Lokaloxidierung von Silizium mit Isolierungsverfahren durch maskierte Seitenflächen

Info

Publication number
DE69510866T2
DE69510866T2 DE69510866T DE69510866T DE69510866T2 DE 69510866 T2 DE69510866 T2 DE 69510866T2 DE 69510866 T DE69510866 T DE 69510866T DE 69510866 T DE69510866 T DE 69510866T DE 69510866 T2 DE69510866 T2 DE 69510866T2
Authority
DE
Germany
Prior art keywords
silicon
side surfaces
local oxidation
masked side
insulation processes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69510866T
Other languages
English (en)
Other versions
DE69510866D1 (de
Inventor
Tzu-Yin Chiu
Te-Yin Mark Liu
Frank Michael Erceg
Kenneth Gordon Moerschel
Michael Allen Prozonic
Janmye Sung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69510866D1 publication Critical patent/DE69510866D1/de
Publication of DE69510866T2 publication Critical patent/DE69510866T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
DE69510866T 1994-06-06 1995-05-24 Lokaloxidierung von Silizium mit Isolierungsverfahren durch maskierte Seitenflächen Expired - Fee Related DE69510866T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US25408894A 1994-06-06 1994-06-06

Publications (2)

Publication Number Publication Date
DE69510866D1 DE69510866D1 (de) 1999-08-26
DE69510866T2 true DE69510866T2 (de) 2000-01-13

Family

ID=22962883

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69510866T Expired - Fee Related DE69510866T2 (de) 1994-06-06 1995-05-24 Lokaloxidierung von Silizium mit Isolierungsverfahren durch maskierte Seitenflächen

Country Status (5)

Country Link
US (1) US5470783A (de)
EP (1) EP0687003B1 (de)
JP (1) JPH07335638A (de)
KR (1) KR100344491B1 (de)
DE (1) DE69510866T2 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3542189B2 (ja) * 1995-03-08 2004-07-14 株式会社ルネサステクノロジ 半導体装置の製造方法及び半導体装置
US5795809A (en) * 1995-05-25 1998-08-18 Advanced Micro Devices, Inc. Semiconductor wafer fabrication process including gettering utilizing a combined oxidation technique
US6835634B1 (en) 1995-08-25 2004-12-28 Micron Technology, Inc. Streamlined field isolation process
US5612248A (en) * 1995-10-11 1997-03-18 Micron Technology, Inc. Method for forming field oxide or other insulators during the formation of a semiconductor device
US5702976A (en) 1995-10-24 1997-12-30 Micron Technology, Inc. Shallow trench isolation using low dielectric constant insulator
US5780353A (en) * 1996-03-28 1998-07-14 Advanced Micro Devices, Inc. Method of doping trench sidewalls before trench etching
US5646063A (en) * 1996-03-28 1997-07-08 Advanced Micro Devices, Inc. Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device
US5904543A (en) * 1996-03-28 1999-05-18 Advanced Micro Devices, Inc Method for formation of offset trench isolation by the use of disposable spacer and trench oxidation
US5861104A (en) * 1996-03-28 1999-01-19 Advanced Micro Devices Trench isolation with rounded top and bottom corners and edges
US6097072A (en) * 1996-03-28 2000-08-01 Advanced Micro Devices Trench isolation with suppressed parasitic edge transistors
US5658822A (en) * 1996-03-29 1997-08-19 Vanguard International Semiconductor Corporation Locos method with double polysilicon/silicon nitride spacer
US5742090A (en) * 1996-04-04 1998-04-21 Advanced Micro Devices, Inc. Narrow width trenches for field isolation in integrated circuits
US5777370A (en) * 1996-06-12 1998-07-07 Advanced Micro Devices, Inc. Trench isolation of field effect transistors
US5874317A (en) * 1996-06-12 1999-02-23 Advanced Micro Devices, Inc. Trench isolation for integrated circuits
KR100189733B1 (ko) * 1996-07-22 1999-06-01 구본준 반도체장치의 소자분리막 형성방법
US5834360A (en) * 1996-07-31 1998-11-10 Stmicroelectronics, Inc. Method of forming an improved planar isolation structure in an integrated circuit
US5652177A (en) * 1996-08-22 1997-07-29 Chartered Semiconductor Manufacturing Pte Ltd Method for fabricating a planar field oxide region
US5753962A (en) * 1996-09-16 1998-05-19 Micron Technology, Inc. Texturized polycrystalline silicon to aid field oxide formation
US5891788A (en) * 1996-11-14 1999-04-06 Micron Technology, Inc. Locus isolation technique using high pressure oxidation (hipox) and protective spacers
US5882982A (en) * 1997-01-16 1999-03-16 Vlsi Technology, Inc. Trench isolation method
US5789305A (en) * 1997-01-27 1998-08-04 Chartered Semiconductor Manufacturing Ltd. Locos with bird's beak suppression by a nitrogen implantation
US5721174A (en) * 1997-02-03 1998-02-24 Chartered Semiconductor Manufacturing Pte Ltd Narrow deep trench isolation process with trench filling by oxidation
US5763316A (en) * 1997-02-19 1998-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate isolation process to minimize junction leakage
US6184105B1 (en) 1997-05-22 2001-02-06 Advanced Micro Devices Method for post transistor isolation
US6455394B1 (en) 1998-03-13 2002-09-24 Micron Technology, Inc. Method for trench isolation by selective deposition of low temperature oxide films
US5834359A (en) * 1997-08-29 1998-11-10 Vanguard International Semiconductor Corporation Method of forming an isolation region in a semiconductor substrate
US6071793A (en) * 1998-02-02 2000-06-06 Chartered Semiconductor Manufacturing Ltd. Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect
US6214696B1 (en) * 1998-04-22 2001-04-10 Texas Instruments - Acer Incorporated Method of fabricating deep-shallow trench isolation
US6444539B1 (en) * 1998-05-20 2002-09-03 Advanced Micro Devices, Inc. Method for producing a shallow trench isolation filled with thermal oxide
US6110793A (en) * 1998-06-24 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits
US6781212B1 (en) * 1998-08-31 2004-08-24 Micron Technology, Inc Selectively doped trench device isolation
US6503813B1 (en) 2000-06-16 2003-01-07 International Business Machines Corporation Method and structure for forming a trench in a semiconductor substrate
TWI229390B (en) * 2003-11-14 2005-03-11 Promos Technologies Inc Device structure of a MOSFET and method of forming the same
DE10361697B4 (de) * 2003-12-30 2011-08-11 Infineon Technologies AG, 81669 Verfahren zum Herstellen einer Grabenstruktur mit Oxidationsauskleidung, zum Herstellen einer integrierten Halbleiterschaltungsanordnung oder eines Chips, zum Herstellen eines Halbleiterbauelements sowie mit diesem Verfahren hergestellte integrierte Halbleiterschaltungsanordnung, hergestellter Chip, hergestelltes Halbleiterbauelement
TW200919593A (en) * 2007-10-18 2009-05-01 Asia Pacific Microsystems Inc Elements and modules with micro caps and wafer level packaging method thereof
US20090184402A1 (en) * 2008-01-22 2009-07-23 United Microelectronics Corp. Method of fabricating a shallow trench isolation structure including forming a second liner covering the corner of the trench and first liner.

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4563227A (en) * 1981-12-08 1986-01-07 Matsushita Electric Industrial Co., Ltd. Method for manufacturing a semiconductor device
US4398992A (en) * 1982-05-20 1983-08-16 Hewlett-Packard Company Defect free zero oxide encroachment process for semiconductor fabrication
NL187373C (nl) * 1982-10-08 1991-09-02 Philips Nv Werkwijze voor vervaardiging van een halfgeleiderinrichting.
JPS607146A (ja) * 1983-06-25 1985-01-14 Toshiba Corp 半導体装置の製造方法
JPS6062135A (ja) * 1983-09-14 1985-04-10 Toshiba Corp 半導体装置の製造方法
JPS60177646A (ja) * 1984-02-24 1985-09-11 Oki Electric Ind Co Ltd 半導体集積回路装置の製造方法
US4580330A (en) * 1984-06-15 1986-04-08 Texas Instruments Incorporated Integrated circuit isolation
JPS61214536A (ja) * 1985-03-20 1986-09-24 Hitachi Ltd 半導体装置の製造方法
US4986879A (en) * 1987-06-15 1991-01-22 Ncr Corporation Structure and process for forming semiconductor field oxide using a sealing sidewall of consumable nitride
US4923563A (en) * 1987-06-15 1990-05-08 Ncr Corporation Semiconductor field oxide formation process using a sealing sidewall of consumable nitride
JPH0199234A (ja) * 1987-10-13 1989-04-18 Matsushita Electric Ind Co Ltd 分離領域形成方法
US5248350A (en) * 1990-11-30 1993-09-28 Ncr Corporation Structure for improving gate oxide integrity for a semiconductor formed by a recessed sealed sidewall field oxidation process
FR2672731A1 (fr) * 1991-02-07 1992-08-14 France Telecom Procede d'oxydation localisee enterree d'un substrat de silicium et circuit integre correspondant.
EP0502663B1 (de) * 1991-03-04 2001-09-05 NCR International, Inc. Verfahren zur Herstellung einer Halbleiteranordnung mit Isolationszonen in einem Halbleitersubstrat
US5246537A (en) * 1992-04-30 1993-09-21 Motorola, Inc. Method of forming recessed oxide isolation

Also Published As

Publication number Publication date
EP0687003A1 (de) 1995-12-13
EP0687003B1 (de) 1999-07-21
JPH07335638A (ja) 1995-12-22
KR100344491B1 (ko) 2002-12-02
KR960002749A (ko) 1996-01-26
US5470783A (en) 1995-11-28
DE69510866D1 (de) 1999-08-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee