DE69435327D1 - Lade-/Speicherfunktionseinheiten und Datencachespeicher für Mikroprozessoren - Google Patents
Lade-/Speicherfunktionseinheiten und Datencachespeicher für MikroprozessorenInfo
- Publication number
- DE69435327D1 DE69435327D1 DE69435327T DE69435327T DE69435327D1 DE 69435327 D1 DE69435327 D1 DE 69435327D1 DE 69435327 T DE69435327 T DE 69435327T DE 69435327 T DE69435327 T DE 69435327T DE 69435327 D1 DE69435327 D1 DE 69435327D1
- Authority
- DE
- Germany
- Prior art keywords
- microprocessors
- load
- functional units
- data cache
- store functional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/146,376 US5878245A (en) | 1993-10-29 | 1993-10-29 | High performance load/store functional unit and data cache |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69435327D1 true DE69435327D1 (de) | 2011-01-13 |
Family
ID=22517097
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69435327T Expired - Lifetime DE69435327D1 (de) | 1993-10-29 | 1994-09-20 | Lade-/Speicherfunktionseinheiten und Datencachespeicher für Mikroprozessoren |
DE69433339T Expired - Lifetime DE69433339T2 (de) | 1993-10-29 | 1994-09-20 | Lade-/Speicherfunktionseinheiten und Datencachespeicher für Mikroprozessoren |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69433339T Expired - Lifetime DE69433339T2 (de) | 1993-10-29 | 1994-09-20 | Lade-/Speicherfunktionseinheiten und Datencachespeicher für Mikroprozessoren |
Country Status (4)
Country | Link |
---|---|
US (2) | US5878245A (de) |
EP (2) | EP0952517B1 (de) |
JP (1) | JPH07182167A (de) |
DE (2) | DE69435327D1 (de) |
Families Citing this family (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6813699B1 (en) | 1995-06-02 | 2004-11-02 | Transmeta Corporation | Speculative address translation for processor using segmentation and optional paging |
US5781789A (en) * | 1995-08-31 | 1998-07-14 | Advanced Micro Devices, Inc. | Superscaler microprocessor employing a parallel mask decoder |
US5694565A (en) * | 1995-09-11 | 1997-12-02 | International Business Machines Corporation | Method and device for early deallocation of resources during load/store multiple operations to allow simultaneous dispatch/execution of subsequent instructions |
US5958042A (en) | 1996-06-11 | 1999-09-28 | Sun Microsystems, Inc. | Grouping logic circuit in a pipelined superscalar processor |
USRE38599E1 (en) * | 1996-06-11 | 2004-09-21 | Sun Microsystems, Inc. | Pipelined instruction dispatch unit in a superscalar processor |
KR19990076967A (ko) * | 1996-11-04 | 1999-10-25 | 요트.게.아. 롤페즈 | 처리 장치 및 메모리내의 명령 판독 |
US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
US6014737A (en) * | 1997-11-19 | 2000-01-11 | Sony Corporation Of Japan | Method and system for allowing a processor to perform read bypassing while automatically maintaining input/output data integrity |
US6065103A (en) * | 1997-12-16 | 2000-05-16 | Advanced Micro Devices, Inc. | Speculative store buffer |
FR2777370B1 (fr) * | 1998-04-09 | 2000-06-23 | Sgs Thomson Microelectronics | Architecture de dsp optimisee pour les acces memoire |
JP3469469B2 (ja) * | 1998-07-07 | 2003-11-25 | 富士通株式会社 | 情報処理装置 |
US6141747A (en) * | 1998-09-22 | 2000-10-31 | Advanced Micro Devices, Inc. | System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word |
US6223259B1 (en) | 1998-10-30 | 2001-04-24 | Telefonaktiebolaget Lm Ericsson (Publ) | Reducing read cycle of memory read request for data to be partially modified by a pending write request |
US6427191B1 (en) * | 1998-12-31 | 2002-07-30 | Intel Corporation | High performance fully dual-ported, pipelined cache design |
US6446169B1 (en) | 1999-08-31 | 2002-09-03 | Micron Technology, Inc. | SRAM with tag and data arrays for private external microprocessor bus |
US6393534B1 (en) * | 1999-09-27 | 2002-05-21 | Ati International Srl | Scheduler for avoiding bank conflicts in issuing concurrent requests to main memory |
US6477637B1 (en) * | 1999-09-30 | 2002-11-05 | International Business Machines Corporation | Method and apparatus for transporting store requests between functional units within a processor |
US6481251B1 (en) | 1999-10-25 | 2002-11-19 | Advanced Micro Devices, Inc. | Store queue number assignment and tracking |
US6523109B1 (en) | 1999-10-25 | 2003-02-18 | Advanced Micro Devices, Inc. | Store queue multimatch detection |
US6662280B1 (en) | 1999-11-10 | 2003-12-09 | Advanced Micro Devices, Inc. | Store buffer which forwards data based on index and optional way match |
US6591342B1 (en) * | 1999-12-14 | 2003-07-08 | Intel Corporation | Memory disambiguation for large instruction windows |
US6408383B1 (en) | 2000-05-04 | 2002-06-18 | Sun Microsystems, Inc. | Array access boundary check by executing BNDCHK instruction with comparison specifiers |
US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
US6678807B2 (en) * | 2000-12-21 | 2004-01-13 | Intel Corporation | System and method for multiple store buffer forwarding in a system with a restrictive memory model |
US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
US7444531B2 (en) | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US6738792B1 (en) | 2001-03-09 | 2004-05-18 | Advanced Micro Devices, Inc. | Parallel mask generator |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US6928534B2 (en) * | 2002-02-22 | 2005-08-09 | Sun Microsystems, Inc. | Forwarding load data to younger instructions in annex |
US8914590B2 (en) | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
WO2004046931A1 (ja) * | 2002-11-20 | 2004-06-03 | Fujitsu Limited | メモリ制御装置およびストアバイパス制御方法 |
US7073026B2 (en) * | 2002-11-26 | 2006-07-04 | Advanced Micro Devices, Inc. | Microprocessor including cache memory supporting multiple accesses per cycle |
US7415243B2 (en) | 2003-03-27 | 2008-08-19 | Honda Giken Kogyo Kabushiki Kaisha | System, method and computer program product for receiving data from a satellite radio network |
US8041779B2 (en) | 2003-12-15 | 2011-10-18 | Honda Motor Co., Ltd. | Method and system for facilitating the exchange of information between a vehicle and a remote location |
US7643788B2 (en) | 2004-09-22 | 2010-01-05 | Honda Motor Co., Ltd. | Method and system for broadcasting data messages to a vehicle |
US7237065B2 (en) * | 2005-05-24 | 2007-06-26 | Texas Instruments Incorporated | Configurable cache system depending on instruction type |
US7376817B2 (en) | 2005-08-10 | 2008-05-20 | P.A. Semi, Inc. | Partial load/store forward prediction |
US20080140934A1 (en) * | 2006-12-11 | 2008-06-12 | Luick David A | Store-Through L2 Cache Mode |
US7668653B2 (en) * | 2007-05-31 | 2010-02-23 | Honda Motor Co., Ltd. | System and method for selectively filtering and providing event program information |
US8099308B2 (en) | 2007-10-02 | 2012-01-17 | Honda Motor Co., Ltd. | Method and system for vehicle service appointments based on diagnostic trouble codes |
US10387151B2 (en) * | 2007-12-31 | 2019-08-20 | Intel Corporation | Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks |
US7984273B2 (en) | 2007-12-31 | 2011-07-19 | Intel Corporation | System and method for using a mask register to track progress of gathering elements from memory |
US8185721B2 (en) * | 2008-03-04 | 2012-05-22 | Qualcomm Incorporated | Dual function adder for computing a hardware prefetch address and an arithmetic operation value |
US20100250850A1 (en) * | 2009-03-25 | 2010-09-30 | Faraday Technology Corp. | Processor and method for executing load operation and store operation thereof |
US10175990B2 (en) | 2009-12-22 | 2019-01-08 | Intel Corporation | Gathering and scattering multiple data elements |
US10360031B2 (en) * | 2011-10-21 | 2019-07-23 | Intel Corporation | Fast unaligned memory access |
US9128725B2 (en) | 2012-05-04 | 2015-09-08 | Apple Inc. | Load-store dependency predictor content management |
US9600289B2 (en) | 2012-05-30 | 2017-03-21 | Apple Inc. | Load-store dependency predictor PC hashing |
US20140189328A1 (en) * | 2012-12-27 | 2014-07-03 | Tomer WEINER | Power reduction by using on-demand reservation station size |
JP6287544B2 (ja) * | 2014-04-25 | 2018-03-07 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
US9710268B2 (en) | 2014-04-29 | 2017-07-18 | Apple Inc. | Reducing latency for pointer chasing loads |
US9672159B2 (en) * | 2015-07-02 | 2017-06-06 | Arm Limited | Translation buffer unit management |
US10509377B2 (en) | 2015-10-22 | 2019-12-17 | Triatomic Environmental, Inc. | System for monitoring and controlling indoor air quality |
US10209991B2 (en) * | 2016-01-21 | 2019-02-19 | Advanced Micro Devices, Inc. | Instruction set and micro-architecture supporting asynchronous memory access |
US10514925B1 (en) | 2016-01-28 | 2019-12-24 | Apple Inc. | Load speculation recovery |
GB2547893B (en) * | 2016-02-25 | 2018-06-06 | Advanced Risc Mach Ltd | Combining part of an offset with a corresponding part of a base address and comparing with a reference address |
US10437595B1 (en) | 2016-03-15 | 2019-10-08 | Apple Inc. | Load/store dependency predictor optimization for replayed loads |
US10157277B2 (en) | 2016-10-01 | 2018-12-18 | Intel Corporation | Technologies for object-oriented memory management with extended segmentation |
KR20180038875A (ko) * | 2016-10-07 | 2018-04-17 | 삼성전자주식회사 | 데이터 입출력 유닛, 전자 장치 및 그 제어 방법들 |
US10877897B2 (en) * | 2018-11-02 | 2020-12-29 | Intel Corporation | System, apparatus and method for multi-cacheline small object memory tagging |
Family Cites Families (38)
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US3781808A (en) | 1972-10-17 | 1973-12-25 | Ibm | Virtual memory system |
AT354159B (de) | 1975-02-10 | 1979-12-27 | Siemens Ag | Assoziativspeicher mit getrennt assoziierbaren bereichen |
US4155119A (en) * | 1977-09-21 | 1979-05-15 | Sperry Rand Corporation | Method for providing virtual addressing for externally specified addressed input/output operations |
US4161784A (en) | 1978-01-05 | 1979-07-17 | Honeywell Information Systems, Inc. | Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands |
US4453212A (en) * | 1981-07-13 | 1984-06-05 | Burroughs Corporation | Extended address generating apparatus and method |
JPS58133696A (ja) * | 1982-02-03 | 1983-08-09 | Hitachi Ltd | 記憶制御方式 |
US4928223A (en) | 1982-10-06 | 1990-05-22 | Fairchild Semiconductor Corporation | Floating point microprocessor with directable two level microinstructions |
AU3229484A (en) * | 1983-09-07 | 1985-03-14 | Amdahl Corporation | Time shared translation buffer |
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EP0259095A3 (de) * | 1986-08-27 | 1990-02-28 | Amdahl Corporation | Warteschlange für einen Cachespeicher |
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US5056006A (en) * | 1988-09-12 | 1991-10-08 | General Electric Company | Parallel processor with single program storage and sequencer and simultaneous instruction processing |
JP2810068B2 (ja) * | 1988-11-11 | 1998-10-15 | 株式会社日立製作所 | プロセッサシステム、コンピュータシステム及び命令処理方法 |
US5155816A (en) * | 1989-02-10 | 1992-10-13 | Intel Corporation | Pipelined apparatus and method for controlled loading of floating point data in a microprocessor |
US5155820A (en) * | 1989-02-21 | 1992-10-13 | Gibson Glenn A | Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits |
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JP2725450B2 (ja) * | 1989-08-28 | 1998-03-11 | 日本電気株式会社 | マイクロプロセッサ |
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US5226130A (en) * | 1990-02-26 | 1993-07-06 | Nexgen Microsystems | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency |
JP2822588B2 (ja) * | 1990-04-30 | 1998-11-11 | 日本電気株式会社 | キャッシュメモリ装置 |
DE69130588T2 (de) * | 1990-05-29 | 1999-05-27 | National Semiconductor Corp., Santa Clara, Calif. | Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür |
US5325499A (en) * | 1990-09-28 | 1994-06-28 | Tandon Corporation | Computer system including a write protection circuit for preventing illegal write operations and a write poster with improved memory |
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US5467473A (en) * | 1993-01-08 | 1995-11-14 | International Business Machines Corporation | Out of order instruction load and store comparison |
US5454117A (en) * | 1993-08-25 | 1995-09-26 | Nexgen, Inc. | Configurable branch prediction for a processor performing speculative execution |
IE80854B1 (en) | 1993-08-26 | 1999-04-07 | Intel Corp | Processor ordering consistency for a processor performing out-of-order instruction execution |
US5434987A (en) * | 1993-09-21 | 1995-07-18 | Intel Corporation | Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store |
-
1993
- 1993-10-29 US US08/146,376 patent/US5878245A/en not_active Expired - Lifetime
-
1994
- 1994-09-20 EP EP99115397A patent/EP0952517B1/de not_active Expired - Lifetime
- 1994-09-20 DE DE69435327T patent/DE69435327D1/de not_active Expired - Lifetime
- 1994-09-20 EP EP94306872A patent/EP0651323B1/de not_active Expired - Lifetime
- 1994-09-20 DE DE69433339T patent/DE69433339T2/de not_active Expired - Lifetime
- 1994-10-25 JP JP6260699A patent/JPH07182167A/ja not_active Withdrawn
-
1996
- 1996-08-26 US US08/703,299 patent/US6298423B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69433339T2 (de) | 2004-09-09 |
EP0952517B1 (de) | 2010-12-01 |
JPH07182167A (ja) | 1995-07-21 |
US6298423B1 (en) | 2001-10-02 |
EP0651323B1 (de) | 2003-11-19 |
EP0952517A3 (de) | 1999-11-17 |
US5878245A (en) | 1999-03-02 |
DE69433339D1 (de) | 2003-12-24 |
EP0952517A2 (de) | 1999-10-27 |
EP0651323A1 (de) | 1995-05-03 |
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