DE69619366D1 - Sperr- und eurekasynchronisierungsarchitektur für multiprozessoren - Google Patents

Sperr- und eurekasynchronisierungsarchitektur für multiprozessoren

Info

Publication number
DE69619366D1
DE69619366D1 DE69619366T DE69619366T DE69619366D1 DE 69619366 D1 DE69619366 D1 DE 69619366D1 DE 69619366 T DE69619366 T DE 69619366T DE 69619366 T DE69619366 T DE 69619366T DE 69619366 D1 DE69619366 D1 DE 69619366D1
Authority
DE
Germany
Prior art keywords
eurekasynchronization
multiprocessors
architecture
locking
eurekasynchronization architecture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69619366T
Other languages
English (en)
Other versions
DE69619366T2 (de
Inventor
E Kessler
M Oberlin
M Thorson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cray Research LLC
Original Assignee
Cray Research LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cray Research LLC filed Critical Cray Research LLC
Publication of DE69619366D1 publication Critical patent/DE69619366D1/de
Application granted granted Critical
Publication of DE69619366T2 publication Critical patent/DE69619366T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/52Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
DE69619366T 1995-05-25 1996-05-24 Sperr- und eurekasynchronisierungsarchitektur für multiprozessoren Expired - Lifetime DE69619366T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/450,251 US5721921A (en) 1995-05-25 1995-05-25 Barrier and eureka synchronization architecture for multiprocessors
PCT/US1996/007843 WO1996037834A1 (en) 1995-05-25 1996-05-24 Barrier and eureka synchronization architecture for multiprocessors

Publications (2)

Publication Number Publication Date
DE69619366D1 true DE69619366D1 (de) 2002-03-28
DE69619366T2 DE69619366T2 (de) 2002-11-28

Family

ID=23787346

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69619366T Expired - Lifetime DE69619366T2 (de) 1995-05-25 1996-05-24 Sperr- und eurekasynchronisierungsarchitektur für multiprozessoren

Country Status (4)

Country Link
US (1) US5721921A (de)
EP (1) EP0829047B1 (de)
DE (1) DE69619366T2 (de)
WO (1) WO1996037834A1 (de)

Families Citing this family (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3532037B2 (ja) * 1996-07-31 2004-05-31 富士通株式会社 並列計算機
US5991764A (en) * 1997-03-12 1999-11-23 International Business Machines Corporation Data structure specifying differing fan-in tree and fan-out tree computation patterns supporting a generic reduction object for data parallelism
US6230252B1 (en) 1997-11-17 2001-05-08 Silicon Graphics, Inc. Hybrid hypercube/torus architecture
US6085303A (en) * 1997-11-17 2000-07-04 Cray Research, Inc. Seralized race-free virtual barrier network
US6101181A (en) * 1997-11-17 2000-08-08 Cray Research Inc. Virtual channel assignment in large torus systems
US6216174B1 (en) * 1998-09-29 2001-04-10 Silicon Graphics, Inc. System and method for fast barrier synchronization
US6272136B1 (en) * 1998-11-16 2001-08-07 Sun Microsystems, Incorporated Pseudo-interface between control and switching modules of a data packet switching and load balancing system
US20140325175A1 (en) * 2013-04-29 2014-10-30 Pact Xpp Technologies Ag Pipeline configuration protocol and configuration unit communication
US6349378B1 (en) * 1999-03-31 2002-02-19 U.S. Philips Corporation Data processing using various data processors
EP1228440B1 (de) 1999-06-10 2017-04-05 PACT XPP Technologies AG Sequenz-partitionierung auf zellstrukturen
US6751698B1 (en) * 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
US6674720B1 (en) 1999-09-29 2004-01-06 Silicon Graphics, Inc. Age-based network arbitration system and method
JP3571976B2 (ja) * 1999-11-08 2004-09-29 富士通株式会社 デバッグ装置及び方法並びにプログラム記録媒体
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
EP1381959A4 (de) * 2001-02-24 2008-10-29 Ibm Globales baumnetzwerk für datenverarbeitungsstrukturen
CA2437035C (en) * 2001-02-24 2009-01-06 International Business Machines Corporation Global interrupt and barrier networks
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
US9411532B2 (en) 2001-09-07 2016-08-09 Pact Xpp Technologies Ag Methods and systems for transferring data between a processing device and external devices
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US7251222B2 (en) * 2001-05-15 2007-07-31 Motorola, Inc. Procedures for merging the mediation device protocol with a network layer protocol
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US7100021B1 (en) * 2001-10-16 2006-08-29 Cisco Technology, Inc. Barrier synchronization mechanism for processors of a systolic array
US6986022B1 (en) * 2001-10-16 2006-01-10 Cisco Technology, Inc. Boundary synchronization mechanism for a processor of a systolic array
US8626957B2 (en) * 2003-08-22 2014-01-07 International Business Machines Corporation Collective network for computer structures
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US7577816B2 (en) * 2003-08-18 2009-08-18 Cray Inc. Remote translation mechanism for a multinode system
AU2003289844A1 (en) 2002-09-06 2004-05-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7366873B1 (en) 2003-08-18 2008-04-29 Cray, Inc. Indirectly addressed vector load-operate-store method and apparatus
US7543133B1 (en) 2003-08-18 2009-06-02 Cray Inc. Latency tolerant distributed shared memory multiprocessor computer
US7503048B1 (en) 2003-08-18 2009-03-10 Cray Incorporated Scheduling synchronization of programs running as streams on multiple processors
US7379424B1 (en) 2003-08-18 2008-05-27 Cray Inc. Systems and methods for routing packets in multiprocessor computer systems
US7519771B1 (en) 2003-08-18 2009-04-14 Cray Inc. System and method for processing memory instructions using a forced order queue
US7334110B1 (en) 2003-08-18 2008-02-19 Cray Inc. Decoupled scalar/vector computer architecture system and method
US7421565B1 (en) * 2003-08-18 2008-09-02 Cray Inc. Method and apparatus for indirectly addressed vector load-add -store across multi-processors
US7437521B1 (en) 2003-08-18 2008-10-14 Cray Inc. Multistream processing memory-and barrier-synchronization method and apparatus
US8307194B1 (en) 2003-08-18 2012-11-06 Cray Inc. Relaxed memory consistency model
US7735088B1 (en) 2003-08-18 2010-06-08 Cray Inc. Scheduling synchronization of programs running as streams on multiple processors
US8001280B2 (en) * 2004-07-19 2011-08-16 International Business Machines Corporation Collective network for computer structures
JP4168281B2 (ja) * 2004-09-16 2008-10-22 日本電気株式会社 並列処理システム、インタコネクションネットワーク、ノード及びネットワーク制御プログラム
US7478769B1 (en) 2005-03-09 2009-01-20 Cray Inc. Method and apparatus for cooling electronic components
JP4372043B2 (ja) * 2005-05-12 2009-11-25 株式会社ソニー・コンピュータエンタテインメント コマンド実行制御装置、コマンド実行指示装置およびコマンド実行制御方法
US7584342B1 (en) 2005-12-15 2009-09-01 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue
US7788468B1 (en) * 2005-12-15 2010-08-31 Nvidia Corporation Synchronization of threads in a cooperative thread array
US7861060B1 (en) 2005-12-15 2010-12-28 Nvidia Corporation Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior
US20080005357A1 (en) * 2006-06-30 2008-01-03 Microsoft Corporation Synchronizing dataflow computations, particularly in multi-processor setting
GB0613289D0 (en) * 2006-07-04 2006-08-16 Imagination Tech Ltd Synchronisation of execution threads on a multi-threaded processor
US20080115139A1 (en) * 2006-10-27 2008-05-15 Todd Alan Inglett Barrier-based access to a shared resource in a massively parallel computer system
US8108659B1 (en) 2006-11-03 2012-01-31 Nvidia Corporation Controlling access to memory resources shared among parallel synchronizable threads
US8478834B2 (en) 2007-07-12 2013-07-02 International Business Machines Corporation Low latency, high bandwidth data communications between compute nodes in a parallel computer
US20090031001A1 (en) * 2007-07-27 2009-01-29 Archer Charles J Repeating Direct Memory Access Data Transfer Operations for Compute Nodes in a Parallel Computer
US8959172B2 (en) * 2007-07-27 2015-02-17 International Business Machines Corporation Self-pacing direct memory access data transfer operations for compute nodes in a parallel computer
US7624107B1 (en) 2007-08-09 2009-11-24 Nvidia Corporation Radix sort algorithm for graphics processing units
US7689541B1 (en) 2007-08-09 2010-03-30 Nvidia Corporation Reordering data using a series of offsets
US8094157B1 (en) 2007-08-09 2012-01-10 Nvidia Corporation Performing an occurence count of radices
US9225545B2 (en) * 2008-04-01 2015-12-29 International Business Machines Corporation Determining a path for network traffic between nodes in a parallel computer
US9009350B2 (en) * 2008-04-01 2015-04-14 International Business Machines Corporation Determining a path for network traffic between nodes in a parallel computer
US8209489B2 (en) * 2008-10-22 2012-06-26 International Business Machines Corporation Victim cache prefetching
US8347037B2 (en) * 2008-10-22 2013-01-01 International Business Machines Corporation Victim cache replacement
US8499124B2 (en) * 2008-12-16 2013-07-30 International Business Machines Corporation Handling castout cache lines in a victim cache
US8225045B2 (en) * 2008-12-16 2012-07-17 International Business Machines Corporation Lateral cache-to-cache cast-in
US8489819B2 (en) * 2008-12-19 2013-07-16 International Business Machines Corporation Victim cache lateral castout targeting
US8949540B2 (en) * 2009-03-11 2015-02-03 International Business Machines Corporation Lateral castout (LCO) of victim cache line in data-invalid state
US8131935B2 (en) * 2009-04-07 2012-03-06 International Business Machines Corporation Virtual barrier synchronization cache
US8095733B2 (en) * 2009-04-07 2012-01-10 International Business Machines Corporation Virtual barrier synchronization cache castout election
US8327073B2 (en) * 2009-04-09 2012-12-04 International Business Machines Corporation Empirically based dynamic control of acceptance of victim cache lateral castouts
US8347036B2 (en) * 2009-04-09 2013-01-01 International Business Machines Corporation Empirically based dynamic control of transmission of victim cache lateral castouts
US8312220B2 (en) * 2009-04-09 2012-11-13 International Business Machines Corporation Mode-based castout destination selection
US8510738B2 (en) 2009-08-20 2013-08-13 Microsoft Corporation Preventing unnecessary context switching by employing an indicator associated with a lock on a resource
US9189403B2 (en) * 2009-12-30 2015-11-17 International Business Machines Corporation Selective cache-to-cache lateral castouts
US8544026B2 (en) * 2010-02-09 2013-09-24 International Business Machines Corporation Processing data communications messages with input/output control blocks
US8949453B2 (en) 2010-11-30 2015-02-03 International Business Machines Corporation Data communications in a parallel active messaging interface of a parallel computer
US8904118B2 (en) 2011-01-07 2014-12-02 International Business Machines Corporation Mechanisms for efficient intra-die/intra-chip collective messaging
US20120179896A1 (en) 2011-01-10 2012-07-12 International Business Machines Corporation Method and apparatus for a hierarchical synchronization barrier in a multi-node system
US9195550B2 (en) 2011-02-03 2015-11-24 International Business Machines Corporation Method for guaranteeing program correctness using fine-grained hardware speculative execution
US9189283B2 (en) * 2011-03-03 2015-11-17 Hewlett-Packard Development Company, L.P. Task launching on hardware resource for client
US8738830B2 (en) 2011-03-03 2014-05-27 Hewlett-Packard Development Company, L.P. Hardware interrupt processing circuit
US9645823B2 (en) 2011-03-03 2017-05-09 Hewlett-Packard Development Company, L.P. Hardware controller to choose selected hardware entity and to execute instructions in relation to selected hardware entity
JP5568048B2 (ja) * 2011-04-04 2014-08-06 株式会社日立製作所 並列計算機システム、およびプログラム
US8949328B2 (en) 2011-07-13 2015-02-03 International Business Machines Corporation Performing collective operations in a distributed processing system
US8930962B2 (en) 2012-02-22 2015-01-06 International Business Machines Corporation Processing unexpected messages at a compute node of a parallel computer
US20130247069A1 (en) * 2012-03-15 2013-09-19 International Business Machines Corporation Creating A Checkpoint Of A Parallel Application Executing In A Parallel Computer That Supports Computer Hardware Accelerated Barrier Operations
US9326042B2 (en) * 2012-06-11 2016-04-26 Samsung Electronics Co., Ltd. Routing method for inter/intra-domain in content centric network
US20130339481A1 (en) * 2012-06-11 2013-12-19 Samsung Electronics Co., Ltd. Method for content discovery of node in intra-domain and inter-domain in content centric network and node therefor
JP5994601B2 (ja) * 2012-11-27 2016-09-21 富士通株式会社 並列計算機、並列計算機の制御プログラム及び並列計算機の制御方法
EP2929434B1 (de) 2012-12-06 2019-01-16 Coherent Logix Incorporated Verarbeitungssystem mit synchronisationsbefehlen
US9953074B2 (en) 2014-01-31 2018-04-24 Sap Se Safe synchronization of parallel data operator trees

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814979A (en) * 1981-04-01 1989-03-21 Teradata Corporation Network to transmit prioritized subtask pockets to dedicated processors
US4933933A (en) * 1986-12-19 1990-06-12 The California Institute Of Technology Torus routing chip
US4833638A (en) * 1986-12-23 1989-05-23 Bell Communications Research, Inc. Parallel processing state alignment
US5105424A (en) * 1988-06-02 1992-04-14 California Institute Of Technology Inter-computer message routing system with each computer having separate routinng automata for each dimension of the network
DE68927946T2 (de) * 1988-08-02 1997-10-16 Philips Electronics Nv Verfahren und Vorrichtung für die Synchronisierung von parallelen Prozessoren unter Verwendung einer unscharf definierten Sperre
US5036459A (en) * 1989-03-09 1991-07-30 U.S. Philips Corporation Multi-processor computer system with distributed memory and an interprocessor communication mechanism, and method for operating such mechanism
JP3072646B2 (ja) * 1989-03-20 2000-07-31 富士通株式会社 並列計算機間通信制御方式
US5161156A (en) * 1990-02-02 1992-11-03 International Business Machines Corporation Multiprocessing packet switching connection system having provision for error correction and recovery
GB9019025D0 (en) * 1990-08-31 1990-10-17 Ncr Co Work station having multiprocessing capability
DE69130630T2 (de) * 1990-09-14 1999-09-09 Hitachi Ltd Synchrones Verfahren und Gerät für Prozessoren
US5365228A (en) * 1991-03-29 1994-11-15 International Business Machines Corporation SYNC-NET- a barrier synchronization apparatus for multi-stage networks
EP0570729A3 (en) * 1992-05-22 1994-07-20 Ibm Apap i/o programmable router
US5434995A (en) * 1993-12-10 1995-07-18 Cray Research, Inc. Barrier synchronization for distributed memory massively parallel processing systems

Also Published As

Publication number Publication date
EP0829047A1 (de) 1998-03-18
DE69619366T2 (de) 2002-11-28
EP0829047B1 (de) 2002-02-20
WO1996037834A1 (en) 1996-11-28
US5721921A (en) 1998-02-24

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