DE69433621D1 - Geraet zur verarbeitung von befehlen in einem rechnersystem - Google Patents

Geraet zur verarbeitung von befehlen in einem rechnersystem

Info

Publication number
DE69433621D1
DE69433621D1 DE69433621T DE69433621T DE69433621D1 DE 69433621 D1 DE69433621 D1 DE 69433621D1 DE 69433621 T DE69433621 T DE 69433621T DE 69433621 T DE69433621 T DE 69433621T DE 69433621 D1 DE69433621 D1 DE 69433621D1
Authority
DE
Germany
Prior art keywords
computer system
processing commands
commands
processing
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69433621T
Other languages
English (en)
Other versions
DE69433621T2 (de
Inventor
S Joshi
Paul Rodman
Yan-Tek Hsu
R Nofal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
MIPS Tech LLC
Original Assignee
Toshiba Corp
MIPS Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, MIPS Technologies Inc filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69433621D1 publication Critical patent/DE69433621D1/de
Publication of DE69433621T2 publication Critical patent/DE69433621T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
DE69433621T 1993-12-15 1994-12-15 Geraet zur verarbeitung von befehlen in einem rechnersystem Expired - Lifetime DE69433621T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/168,744 US5604909A (en) 1993-12-15 1993-12-15 Apparatus for processing instructions in a computing system
US168744 1993-12-15
PCT/JP1994/002112 WO1995016954A1 (fr) 1993-12-15 1994-12-15 Circuit de traitement d'instructions dans un systeme informatique

Publications (2)

Publication Number Publication Date
DE69433621D1 true DE69433621D1 (de) 2005-01-27
DE69433621T2 DE69433621T2 (de) 2005-05-12

Family

ID=22612755

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69433621T Expired - Lifetime DE69433621T2 (de) 1993-12-15 1994-12-15 Geraet zur verarbeitung von befehlen in einem rechnersystem

Country Status (8)

Country Link
US (4) US5604909A (de)
EP (2) EP0690373B1 (de)
JP (1) JP2815237B2 (de)
KR (1) KR100212204B1 (de)
CN (2) CN1267819C (de)
DE (1) DE69433621T2 (de)
HK (1) HK1013153A1 (de)
WO (1) WO1995016954A1 (de)

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734874A (en) * 1994-04-29 1998-03-31 Sun Microsystems, Inc. Central processing unit with integrated graphics functions
US5778250A (en) * 1994-05-23 1998-07-07 Cirrus Logic, Inc. Method and apparatus for dynamically adjusting the number of stages of a multiple stage pipeline
EP1278125A2 (de) 1994-10-14 2003-01-22 MIPS Technologies, Inc. Indexierung und Multiplexierung von verschachtelten Cache-Speichermatrixen
WO1996012231A1 (en) 1994-10-14 1996-04-25 Silicon Graphics, Inc. A translation buffer for detecting and preventing conflicting virtual addresses from being stored therein
US5991869A (en) * 1995-04-12 1999-11-23 Advanced Micro Devices, Inc. Superscalar microprocessor including a high speed instruction alignment unit
GB9521977D0 (en) * 1995-10-26 1996-01-03 Sgs Thomson Microelectronics Cache memory
GB9521980D0 (en) * 1995-10-26 1996-01-03 Sgs Thomson Microelectronics Branch target buffer
GB9521955D0 (en) * 1995-10-26 1996-01-03 Sgs Thomson Microelectronics Cache memory
US6216213B1 (en) * 1996-06-07 2001-04-10 Motorola, Inc. Method and apparatus for compression, decompression, and execution of program code
WO1998002798A1 (en) * 1996-07-16 1998-01-22 Advanced Micro Devices, Inc. A superscalar microprocesser including a high speed instruction alignment unit
DE19630861A1 (de) * 1996-07-31 1998-02-05 Philips Patentverwaltung Datenverarbeitungseinrichtung mit einem Mikroprozessor und einer zusätzlichen Recheneinheit
US5859992A (en) * 1997-03-12 1999-01-12 Advanced Micro Devices, Inc. Instruction alignment using a dispatch list and a latch list
US6157999A (en) * 1997-06-03 2000-12-05 Motorola Inc. Data processing system having a synchronizing link stack and method thereof
US5935238A (en) * 1997-06-19 1999-08-10 Sun Microsystems, Inc. Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles
US5964869A (en) * 1997-06-19 1999-10-12 Sun Microsystems, Inc. Instruction fetch mechanism with simultaneous prediction of control-flow instructions
US6157988A (en) * 1997-08-01 2000-12-05 Micron Technology, Inc. Method and apparatus for high performance branching in pipelined microsystems
US6185676B1 (en) * 1997-09-30 2001-02-06 Intel Corporation Method and apparatus for performing early branch prediction in a microprocessor
US6243805B1 (en) * 1998-08-11 2001-06-05 Advanced Micro Devices, Inc. Programming paradigm and microprocessor architecture for exact branch targeting
US6289442B1 (en) * 1998-10-05 2001-09-11 Advanced Micro Devices, Inc. Circuit and method for tagging and invalidating speculatively executed instructions
US6442674B1 (en) * 1998-12-30 2002-08-27 Intel Corporation Method and system for bypassing a fill buffer located along a first instruction path
US6957327B1 (en) * 1998-12-31 2005-10-18 Stmicroelectronics, Inc. Block-based branch target buffer
US6185672B1 (en) * 1999-02-19 2001-02-06 Advanced Micro Devices, Inc. Method and apparatus for instruction queue compression
EP1050810A1 (de) 1999-05-03 2000-11-08 STMicroelectronics SA Rechnersystem mit mehreren funktionellen Einheiten
US6546478B1 (en) 1999-10-14 2003-04-08 Advanced Micro Devices, Inc. Line predictor entry with location pointers and control information for corresponding instructions in a cache line
KR20020039689A (ko) * 1999-10-14 2002-05-27 토토라노 제이. 빈센트 정렬정보를 캐쉬하는 장치 및 방법
US6636959B1 (en) 1999-10-14 2003-10-21 Advanced Micro Devices, Inc. Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition
US6647490B2 (en) 1999-10-14 2003-11-11 Advanced Micro Devices, Inc. Training line predictor for branch targets
US6591361B1 (en) 1999-12-28 2003-07-08 International Business Machines Corporation Method and apparatus for converting data into different ordinal types
US7149883B1 (en) 2000-03-30 2006-12-12 Intel Corporation Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue
US6701424B1 (en) * 2000-04-07 2004-03-02 Nintendo Co., Ltd. Method and apparatus for efficient loading and storing of vectors
US6859862B1 (en) 2000-04-07 2005-02-22 Nintendo Co., Ltd. Method and apparatus for software management of on-chip cache
US6857061B1 (en) 2000-04-07 2005-02-15 Nintendo Co., Ltd. Method and apparatus for obtaining a scalar value directly from a vector register
US6484228B2 (en) 2000-04-19 2002-11-19 Motorola, Inc. Method and apparatus for data compression and decompression for a data processor system
DE10043003A1 (de) * 2000-09-01 2002-03-14 Infineon Technologies Ag Programmgesteuerte Einheit
US7139898B1 (en) 2000-11-03 2006-11-21 Mips Technologies, Inc. Fetch and dispatch disassociation apparatus for multistreaming processors
US7035998B1 (en) 2000-11-03 2006-04-25 Mips Technologies, Inc. Clustering stream and/or instruction queues for multi-streaming processors
JP2002318687A (ja) * 2001-04-18 2002-10-31 Fujitsu Ltd 情報処理装置及び計算機システム
JP3851235B2 (ja) * 2002-06-28 2006-11-29 富士通株式会社 分岐予測装置および分岐予測方法
US7131017B2 (en) * 2002-08-16 2006-10-31 Carnegie Mellon University Programmable pipeline fabric having mechanism to terminate signal propagation
US6836833B1 (en) * 2002-10-22 2004-12-28 Mips Technologies, Inc. Apparatus and method for discovering a scratch pad memory configuration
WO2004051449A2 (en) * 2002-12-04 2004-06-17 Koninklijke Philips Electronics N.V. Register file gating to reduce microprocessor power dissipation
US20040111594A1 (en) * 2002-12-05 2004-06-10 International Business Machines Corporation Multithreading recycle and dispatch mechanism
JP3855270B2 (ja) * 2003-05-29 2006-12-06 ソニー株式会社 アンテナ実装方法
US7281120B2 (en) * 2004-03-26 2007-10-09 International Business Machines Corporation Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor
US7363468B2 (en) * 2004-11-18 2008-04-22 International Business Machines Corporation Load address dependency mechanism system and method in a high frequency, low power processor system
US7426631B2 (en) * 2005-02-02 2008-09-16 International Business Machines Corporation Methods and systems for storing branch information in an address table of a processor
DE102005009083B4 (de) * 2005-02-28 2007-05-10 Infineon Technologies Ag Multithread-Prozessor mit einer Synchronisationseinheit und Verfahren zum Betreiben eines solchen
US20060229638A1 (en) * 2005-03-29 2006-10-12 Abrams Robert M Articulating retrieval device
US7461237B2 (en) * 2005-04-20 2008-12-02 Sun Microsystems, Inc. Method and apparatus for suppressing duplicative prefetches for branch target cache lines
US7350056B2 (en) * 2005-09-27 2008-03-25 International Business Machines Corporation Method and apparatus for issuing instructions from an issue queue in an information handling system
US20070198812A1 (en) * 2005-09-27 2007-08-23 Ibm Corporation Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system
US7734901B2 (en) * 2005-10-31 2010-06-08 Mips Technologies, Inc. Processor core and method for managing program counter redirection in an out-of-order processor pipeline
US7711934B2 (en) * 2005-10-31 2010-05-04 Mips Technologies, Inc. Processor core and method for managing branch misprediction in an out-of-order processor pipeline
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US20070204139A1 (en) 2006-02-28 2007-08-30 Mips Technologies, Inc. Compact linked-list-based multi-threaded instruction graduation buffer
US7370178B1 (en) * 2006-07-14 2008-05-06 Mips Technologies, Inc. Method for latest producer tracking in an out-of-order processor, and applications thereof
US20080016326A1 (en) * 2006-07-14 2008-01-17 Mips Technologies, Inc. Latest producer tracking in an out-of-order processor, and applications thereof
US7650465B2 (en) 2006-08-18 2010-01-19 Mips Technologies, Inc. Micro tag array having way selection bits for reducing data cache access power
US7657708B2 (en) * 2006-08-18 2010-02-02 Mips Technologies, Inc. Methods for reducing data cache access power in a processor using way selection bits
US7647475B2 (en) * 2006-09-06 2010-01-12 Mips Technologies, Inc. System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue
US8032734B2 (en) * 2006-09-06 2011-10-04 Mips Technologies, Inc. Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor
US9946547B2 (en) * 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US8078846B2 (en) 2006-09-29 2011-12-13 Mips Technologies, Inc. Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
US7594079B2 (en) 2006-09-29 2009-09-22 Mips Technologies, Inc. Data cache virtual hint way prediction, and applications thereof
US20080082793A1 (en) * 2006-09-29 2008-04-03 Mips Technologies, Inc. Detection and prevention of write-after-write hazards, and applications thereof
US7711935B2 (en) * 2007-04-30 2010-05-04 Netlogic Microsystems, Inc. Universal branch identifier for invalidation of speculative instructions
US8127115B2 (en) * 2009-04-03 2012-02-28 International Business Machines Corporation Group formation with multiple taken branches per group
US9354887B2 (en) * 2010-06-28 2016-05-31 International Business Machines Corporation Instruction buffer bypass of target instruction in response to partial flush
US8937622B2 (en) 2010-09-20 2015-01-20 Qualcomm Incorporated Inter-processor communication techniques in a multiple-processor computing platform
US9280398B2 (en) 2012-01-31 2016-03-08 International Business Machines Corporation Major branch instructions
US9229722B2 (en) 2012-01-31 2016-01-05 International Business Machines Corporation Major branch instructions with transactional memory
US9304932B2 (en) 2012-12-20 2016-04-05 Qualcomm Incorporated Instruction cache having a multi-bit way prediction mask
EP3060983B1 (de) * 2013-10-25 2020-01-08 Advanced Micro Devices, Inc. Bandbreitenerhöhung in einer verzweigungs-vorhersageeinheit und einem level-1-befehlscachespeicher
US10216520B2 (en) * 2014-10-06 2019-02-26 Via Technologies, Inc. Compressing instruction queue for a microprocessor
JP7004905B2 (ja) * 2018-03-26 2022-01-21 富士通株式会社 演算処理装置及び演算処理装置の制御方法
CN109101276B (zh) 2018-08-14 2020-05-05 阿里巴巴集团控股有限公司 在cpu中执行指令的方法

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50152629A (de) * 1974-05-27 1975-12-08
JPS5729153A (en) * 1980-07-29 1982-02-17 Fujitsu Ltd Control system for instruction processing order
JPS57152046A (en) * 1981-03-13 1982-09-20 Mitsubishi Electric Corp Instruction buffer controlling method
JPS58149548A (ja) * 1982-03-02 1983-09-05 Hitachi Ltd メモリ制御方式
JPS5991549A (ja) * 1982-11-17 1984-05-26 Nec Corp 命令バツフアへの命令語格納方式
EP0109655B1 (de) * 1982-11-17 1991-07-24 Nec Corporation Anordnung zum Vorabholen von Befehlen mit Vorhersage einer Verzweigungszieladresse
DE3305693A1 (de) * 1983-02-18 1984-08-30 Nixdorf Computer Ag Schaltungsanordnung zur zwischenspeicherung von befehlsworten
US4635194A (en) * 1983-05-02 1987-01-06 International Business Machines Corporation Instruction buffer bypass apparatus
AU553416B2 (en) * 1984-02-24 1986-07-17 Fujitsu Limited Pipeline processing
US4682284A (en) * 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
US4777587A (en) * 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
IL81762A0 (en) * 1986-04-11 1987-10-20 Symbolics Inc Instruction prefetch unit
EP0312764A3 (de) * 1987-10-19 1991-04-10 International Business Machines Corporation Datenprozessor mit mehrfachen Ausführungseinheiten zur parallelen Ausführung von mehreren Befehlsklassen
US5247628A (en) * 1987-11-30 1993-09-21 International Business Machines Corporation Parallel processor instruction dispatch apparatus with interrupt handler
JPH0769821B2 (ja) * 1988-03-04 1995-07-31 日本電気株式会社 情報処理装置におけるバイパスライン制御方式
JP2810068B2 (ja) * 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
JPH0778735B2 (ja) * 1988-12-05 1995-08-23 松下電器産業株式会社 キャッシュ装置と命令読出し装置
US5113515A (en) * 1989-02-03 1992-05-12 Digital Equipment Corporation Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
EP0394624B1 (de) * 1989-04-24 1997-06-18 International Business Machines Corporation Mehrfachsequenzprozessorsystem
CA2016068C (en) * 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
JPH03139726A (ja) * 1989-10-26 1991-06-13 Hitachi Ltd 命令読出し制御方式
US5121502A (en) * 1989-12-20 1992-06-09 Hewlett-Packard Company System for selectively communicating instructions from memory locations simultaneously or from the same memory locations sequentially to plurality of processing
EP0436341B1 (de) * 1990-01-02 1997-05-07 Motorola, Inc. Verfahren zum sequentiellen Vorabruf von 1-Wort-, 2-Wort oder 3-Wort-Befehlen
US5185868A (en) * 1990-01-16 1993-02-09 Advanced Micro Devices, Inc. Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy
US5283873A (en) * 1990-06-29 1994-02-01 Digital Equipment Corporation Next line prediction apparatus for a pipelined computed system
EP0477598A2 (de) * 1990-09-26 1992-04-01 Siemens Aktiengesellschaft Befehlswerk für einen n Prozessorelemente aufweisenden Prozessor
US5299321A (en) * 1990-12-18 1994-03-29 Oki Electric Industry Co., Ltd. Parallel processing device to operate with parallel execute instructions
JP2877531B2 (ja) * 1991-02-04 1999-03-31 株式会社東芝 並列演算処理装置
JPH04275628A (ja) * 1991-03-01 1992-10-01 Mitsubishi Electric Corp 演算処理装置
DE4211222B4 (de) * 1991-04-05 2009-05-28 Kabushiki Kaisha Toshiba, Kawasaki Abzweigungs-Vorhersage-Vorrichtung und Abzweigungs-Vorhersage-Verfahren für einen Super-Skalar-Prozessor
JP2642529B2 (ja) * 1991-04-30 1997-08-20 株式会社東芝 並列プロセッサーの命令分配処理装置
JPH052484A (ja) * 1991-06-24 1993-01-08 Mitsubishi Electric Corp スーパースカラプロセツサ
CA2107046A1 (en) * 1993-01-08 1994-07-09 James Allan Kahle Method and system for increased instruction dispatch efficiency in superscalar processor system
US5367703A (en) * 1993-01-08 1994-11-22 International Business Machines Corporation Method and system for enhanced branch history prediction accuracy in a superscalar processor system
JP2744882B2 (ja) * 1993-01-15 1998-04-28 インターナショナル・ビジネス・マシーンズ・コーポレイション キューにより命令の実行を制御する装置及び方法
US5680564A (en) * 1995-05-26 1997-10-21 National Semiconductor Corporation Pipelined processor with two tier prefetch buffer structure and method with bypass
US5835746A (en) * 1997-04-21 1998-11-10 Motorola, Inc. Method and apparatus for fetching and issuing dual-word or multiple instructions in a data processing system
US6065110A (en) * 1998-02-09 2000-05-16 International Business Machines Corporation Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue

Also Published As

Publication number Publication date
CN1267819C (zh) 2006-08-02
EP0690373B1 (de) 2004-03-17
EP0690373A1 (de) 1996-01-03
JP2815237B2 (ja) 1998-10-27
US5604909A (en) 1997-02-18
DE69433621T2 (de) 2005-05-12
CN1117765A (zh) 1996-02-28
EP0690373A4 (de) 1997-05-14
US20030033505A1 (en) 2003-02-13
KR100212204B1 (ko) 1999-08-02
US6247124B1 (en) 2001-06-12
CN1492319A (zh) 2004-04-28
EP1320031A2 (de) 2003-06-18
EP1320031A3 (de) 2008-12-17
CN1104680C (zh) 2003-04-02
WO1995016954A1 (fr) 1995-06-22
US5954815A (en) 1999-09-21
KR960701400A (ko) 1996-02-24
HK1013153A1 (en) 1999-08-13
US6691221B2 (en) 2004-02-10

Similar Documents

Publication Publication Date Title
DE69433621D1 (de) Geraet zur verarbeitung von befehlen in einem rechnersystem
DE69424944D1 (de) Datenreduktion in einem system zur analysierung von geometrischen datenbanken
DE69329846T2 (de) Vorrichtung zur Eingabe von Handschriftbefehlen
DE69228582T2 (de) Vorrichtung zur Vermeidung von Prozessorblockierungen in einem Multiprozessorsystem
DE69412392D1 (de) Vorrichtung zur extraktion mit einem superkritischen fluidum
DE3685339D1 (de) Verfahren zur optimierung des operandzugriffs und verarbeitung in einem rechnersystem.
DE69626590T2 (de) Netzwerksteuerungsgerät zur Ausführung von RAID-Operationen in einem Datenverarbeitungssystem
DE68924061D1 (de) Versionskontrolle in einem Datenverarbeitungssystem.
DE69025524D1 (de) Vorrichtung und Verfahren zur Steuerung von Speicherzugriffsanforderungen in einem digitalen Datenverarbeitungssystem
DE69429762D1 (de) Verfahren und Vorrichtung zur Befehlsteuerung in einem Pipelineprozessor
DE69514420D1 (de) Vorrichtung zur Bereitstellung von hörbaren Befehlen oder Zustandsinformationen in einem digitalen Fernsehsystem
DE69418082T2 (de) System und Verfahren zur Vermeidung von Verklemmung in einem Rechner
DE69226093D1 (de) Verfahren und Gerät zur Rechnercode-Verarbeitung in einem Codeübersetzer
DE69228652D1 (de) Verfahren und Vorrichtung zur Durchführung von Submodel-Steuerung in einem Datenverarbeitungssystem
DE68928737D1 (de) Vorrichtung zur handhabung von dokumenten in einem datenverarbeitungssystem
DE69523554T2 (de) Daten-verarbeitungsgerät zur modellierung von produktionsregelsystemen
DE69327270T2 (de) Job-Ausführungsmethode in einem Multiprozessor-System
DE69018259T2 (de) Verfahren und gerät zur verarbeitung von mehr als einem hochgeschwindigkeitssignal mit einem einzigen mikroprozessor-hochgeschwindigkeitseingang.
DE69412670D1 (de) Vorrichtung zur Unterdrückung von falschen Flanken in einem Eingangssignal
DE69128158D1 (de) Verfahren und Gerät zur visuellen Vergleichung von Dateien in einem Datenverarbeitungssystem
DE69414668D1 (de) Vorrichtung zur Auflösung von Reagenzien in einem Sensorsystem
DE69324833D1 (de) Einrichtung und Verfahren zur Übertragungssteuerung in einem Rechnersystem
DE3990616T1 (de) Vorrichtung zur erfassung von verlust oder unerwuenschtem verbrauch in einem rohrsystem
DE9309376U1 (de) Vorrichtung zur Klassifizierung flächiger Gegenstände
DE9320882U1 (de) Vorrichtung zur Vereinzelung von Gegenständen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition