DE69425313D1 - Viterbi-Entzerrer mit Rechenleistungsparendem Trace-Back-Verfahren - Google Patents

Viterbi-Entzerrer mit Rechenleistungsparendem Trace-Back-Verfahren

Info

Publication number
DE69425313D1
DE69425313D1 DE69425313T DE69425313T DE69425313D1 DE 69425313 D1 DE69425313 D1 DE 69425313D1 DE 69425313 T DE69425313 T DE 69425313T DE 69425313 T DE69425313 T DE 69425313T DE 69425313 D1 DE69425313 D1 DE 69425313D1
Authority
DE
Germany
Prior art keywords
trace
computing power
back process
viterbi equalizer
saves computing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69425313T
Other languages
English (en)
Other versions
DE69425313T2 (de
Inventor
David Mark Blaker
Gregory Stephen Ellard
Mahammad Shafiul Mobin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Publication of DE69425313D1 publication Critical patent/DE69425313D1/de
Application granted granted Critical
Publication of DE69425313T2 publication Critical patent/DE69425313T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0059—Convolutional codes
    • H04L1/006—Trellis-coded modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6331—Error control coding in combination with equalisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3961—Arrangements of methods for branch or transition metric calculation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
DE69425313T 1993-11-16 1994-11-09 Viterbi-Entzerrer mit Rechenleistungsparendem Trace-Back-Verfahren Expired - Fee Related DE69425313T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/153,333 US5490178A (en) 1993-11-16 1993-11-16 Power and time saving initial tracebacks

Publications (2)

Publication Number Publication Date
DE69425313D1 true DE69425313D1 (de) 2000-08-24
DE69425313T2 DE69425313T2 (de) 2001-01-04

Family

ID=22546757

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69425313T Expired - Fee Related DE69425313T2 (de) 1993-11-16 1994-11-09 Viterbi-Entzerrer mit Rechenleistungsparendem Trace-Back-Verfahren

Country Status (6)

Country Link
US (1) US5490178A (de)
EP (1) EP0653867B1 (de)
JP (1) JP3256388B2 (de)
KR (1) KR100311837B1 (de)
DE (1) DE69425313T2 (de)
TW (1) TW266356B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2724273B1 (fr) * 1994-09-05 1997-01-03 Sgs Thomson Microelectronics Circuit de traitement de signal pour mettre en oeuvre un algorithme de viterbi
JP3171772B2 (ja) * 1995-08-23 2001-06-04 沖電気工業株式会社 ビタビ復号方法及びビタビ復号装置
US5938790A (en) * 1997-03-04 1999-08-17 Silicon Systems Research Ltd. Sequence error event detection and correction using fixed block digital sum codes
US6009128A (en) * 1997-09-08 1999-12-28 Lucent Technologies, Inc. Metric acceleration on dual MAC processor
US6094739A (en) * 1997-09-24 2000-07-25 Lucent Technologies, Inc. Trellis decoder for real-time video rate decoding and de-interleaving
US6317847B1 (en) * 1998-08-31 2001-11-13 Advanced Micro Devices, Inc. Software read and write tracing using hardware elements
US6591395B1 (en) * 2000-06-18 2003-07-08 Silicon Integrated Systems Corporation Memory reduction techniques in a viterbi decoder
US7661059B2 (en) * 2001-08-06 2010-02-09 Analog Devices, Inc. High performance turbo and Viterbi channel decoding in digital signal processors
AU2002357739A1 (en) * 2001-11-16 2003-06-10 Morpho Technologies Viterbi convolutional coding method and apparatus
US7020830B2 (en) * 2001-12-24 2006-03-28 Agere Systems Inc. High speed add-compare-select operations for use in viterbi decoders
SG125064A1 (en) * 2002-02-15 2006-09-29 Panasonic Singapore Lab Pte Lt Traceback operation in viterbi decoding for rate-k/n convolutional codes
KR100478462B1 (ko) * 2002-05-10 2005-03-23 매그나칩 반도체 유한회사 격자 코드 데이타의 생존 경로 역추적장치
US20040255230A1 (en) * 2003-06-10 2004-12-16 Inching Chen Configurable decoder
CN1957533A (zh) * 2004-05-27 2007-05-02 松下电器产业株式会社 维特比译码装置以及维特比译码方法
GB2475653B (en) * 2007-03-12 2011-07-13 Advanced Risc Mach Ltd Select and insert instructions within data processing systems
TWI729755B (zh) * 2020-04-01 2021-06-01 智原科技股份有限公司 接收器與應用在接收器中的交織碼調變解碼器及相關的解碼方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3789360A (en) * 1972-10-13 1974-01-29 Harris Intertype Corp Convolutional decoder
NZ198844A (en) * 1980-11-14 1984-05-31 Plessey Overseas Digital information transmission: two dimensional code
GB8315363D0 (en) * 1983-06-03 1983-07-06 Gordon J A Decoding errorcorrecting codes
US4583078A (en) * 1984-11-13 1986-04-15 Communications Satellite Corporation Serial Viterbi decoder
US4868830A (en) * 1985-09-27 1989-09-19 California Institute Of Technology Method and apparatus for implementing a traceback maximum-likelihood decoder in a hypercube network
JPS62105531A (ja) * 1985-11-01 1987-05-16 Kokusai Denshin Denwa Co Ltd <Kdd> 逐次復号誤り訂正方式
CA1260143A (en) * 1986-02-24 1989-09-26 Atsushi Yamashita Path trace viterbi decoder
JPS62233933A (ja) * 1986-04-03 1987-10-14 Toshiba Corp ヴイタビ復号法
US4748626A (en) * 1987-01-28 1988-05-31 Racal Data Communications Inc. Viterbi decoder with reduced number of data move operations
JPH0254639A (ja) * 1988-08-19 1990-02-23 Nec Corp 誤り訂正機能付データ変復調装置
US5220570A (en) * 1990-11-30 1993-06-15 The Board Of Trustees Of The Leland Stanford Junior University Programmable viterbi signal processor
FR2686751B1 (fr) * 1992-01-24 1997-03-28 France Telecom Procede de decodage a maximum de vraisemblance a treillis de decodage sous-echantillonne, et dispositif de decodage correspondant.

Also Published As

Publication number Publication date
US5490178A (en) 1996-02-06
KR950016068A (ko) 1995-06-17
JP3256388B2 (ja) 2002-02-12
TW266356B (de) 1995-12-21
EP0653867A1 (de) 1995-05-17
EP0653867B1 (de) 2000-07-19
JPH07202727A (ja) 1995-08-04
DE69425313T2 (de) 2001-01-04
KR100311837B1 (ko) 2001-12-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee