DE69422794D1 - Programmierbare logische Feldstruktur für nichtflüchtige Halbleiterspeicher, insbesondere Flash-EPROMS - Google Patents

Programmierbare logische Feldstruktur für nichtflüchtige Halbleiterspeicher, insbesondere Flash-EPROMS

Info

Publication number
DE69422794D1
DE69422794D1 DE69422794T DE69422794T DE69422794D1 DE 69422794 D1 DE69422794 D1 DE 69422794D1 DE 69422794 T DE69422794 T DE 69422794T DE 69422794 T DE69422794 T DE 69422794T DE 69422794 D1 DE69422794 D1 DE 69422794D1
Authority
DE
Germany
Prior art keywords
volatile semiconductor
field structure
semiconductor memories
logical field
programmable logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69422794T
Other languages
English (en)
Other versions
DE69422794T2 (de
Inventor
Silvia Padoan
Luigi Pascucci
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69422794D1 publication Critical patent/DE69422794D1/de
Publication of DE69422794T2 publication Critical patent/DE69422794T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
DE69422794T 1994-02-18 1994-02-18 Programmierbare logische Feldstruktur für nichtflüchtige Halbleiterspeicher, insbesondere Flash-EPROMS Expired - Fee Related DE69422794T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830072A EP0669720B1 (de) 1994-02-18 1994-02-18 Programmierbare logische Feldstruktur für nichtflüchtige Halbleiterspeicher, insbesondere Flash-EPROMS

Publications (2)

Publication Number Publication Date
DE69422794D1 true DE69422794D1 (de) 2000-03-02
DE69422794T2 DE69422794T2 (de) 2000-06-08

Family

ID=8218384

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69422794T Expired - Fee Related DE69422794T2 (de) 1994-02-18 1994-02-18 Programmierbare logische Feldstruktur für nichtflüchtige Halbleiterspeicher, insbesondere Flash-EPROMS

Country Status (4)

Country Link
US (1) US5559449A (de)
EP (1) EP0669720B1 (de)
JP (1) JP3181009B2 (de)
DE (1) DE69422794T2 (de)

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US5717642A (en) * 1994-02-18 1998-02-10 Sgs-Thomson Microelectronics S.R.L. Load signal generating method and circuit for nonvolatile memories
US6351428B2 (en) 2000-02-29 2002-02-26 Micron Technology, Inc. Programmable low voltage decode circuits with ultra-thin tunnel oxides
US6605961B1 (en) * 2000-02-29 2003-08-12 Micron Technology, Inc. Low voltage PLA's with ultrathin tunnel oxides
US6639835B2 (en) 2000-02-29 2003-10-28 Micron Technology, Inc. Static NVRAM with ultra thin tunnel oxides
US6348812B1 (en) * 2000-07-05 2002-02-19 Elan Research Dynamic programmable logic array that can be reprogrammed and a method of use
KR100441608B1 (ko) * 2002-05-31 2004-07-23 삼성전자주식회사 낸드 플래시 메모리 인터페이스 장치
US7521960B2 (en) * 2003-07-31 2009-04-21 Actel Corporation Integrated circuit including programmable logic and external-device chip-enable override control
US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US7138824B1 (en) * 2004-05-10 2006-11-21 Actel Corporation Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks
US7099189B1 (en) 2004-10-05 2006-08-29 Actel Corporation SRAM cell controlled by non-volatile memory cell
US7116181B2 (en) * 2004-12-21 2006-10-03 Actel Corporation Voltage- and temperature-compensated RC oscillator circuit
US7119398B1 (en) * 2004-12-22 2006-10-10 Actel Corporation Power-up and power-down circuit for system-on-a-chip integrated circuit
US7446378B2 (en) 2004-12-29 2008-11-04 Actel Corporation ESD protection structure for I/O pad subject to both positive and negative voltages
US7541841B2 (en) * 2005-10-18 2009-06-02 Panasonic Corporation Semiconductor integrated circuit
FR2903205A1 (fr) * 2006-06-28 2008-01-04 St Microelectronics Sa Procede de controle du temps d'evaluation d'une machine d'etat
US7280398B1 (en) 2006-08-31 2007-10-09 Micron Technology, Inc. System and memory for sequential multi-plane page memory operations
US8370603B2 (en) 2008-12-23 2013-02-05 Apple Inc. Architecture for address mapping of managed non-volatile memory
US8438453B2 (en) 2009-05-06 2013-05-07 Apple Inc. Low latency read operation for managed non-volatile memory
US8321647B2 (en) * 2009-05-06 2012-11-27 Apple Inc. Multipage preparation commands for non-volatile memory systems
US8495332B2 (en) * 2009-07-24 2013-07-23 Apple Inc. Controller for optimizing throughput of read operations
US8838877B2 (en) * 2009-09-16 2014-09-16 Apple Inc. File system derived metadata for management of non-volatile memory
US8489907B2 (en) 2009-09-16 2013-07-16 Apple Inc. Method of selective power cycling of components in a memory device independently by reducing power to a memory array or memory controller

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4661922A (en) * 1982-12-08 1987-04-28 American Telephone And Telegraph Company Programmed logic array with two-level control timing
US4488229A (en) * 1982-12-08 1984-12-11 At&T Bell Laboratories PLA-Based finite state machine with two-level control timing and same-cycle decision-making capability
US4700088A (en) * 1983-08-05 1987-10-13 Texas Instruments Incorporated Dummy load controlled multilevel logic single clock logic circuit
US4740721A (en) * 1985-10-21 1988-04-26 Western Digital Corporation Programmable logic array with single clock dynamic logic
IT1195119B (it) * 1986-08-04 1988-10-12 Cselt Centro Studi Lab Telecom Perfezionamenti alle schiere logi che programmabili dinamiche a struttura nor nor realizzate in tecnolo gia c mos
JPS6369321A (ja) * 1986-09-11 1988-03-29 Fujitsu Ltd 半導体装置
US4760290A (en) * 1987-05-21 1988-07-26 Vlsi Technology, Inc. Synchronous logic array circuit with dummy signal lines for controlling "AND" array output
JPH0193927A (ja) * 1987-10-06 1989-04-12 Fujitsu Ltd プログラム可能な論理回路
JPH037425A (ja) * 1989-06-05 1991-01-14 Matsushita Electric Ind Co Ltd プログラマブルロジックアレイ
JPH03231515A (ja) * 1990-02-06 1991-10-15 Mitsubishi Electric Corp プログラマブル論理装置
US5136186A (en) * 1991-08-30 1992-08-04 Waferscale Integration, Incorporation Glitch free power-up for a programmable array
US5221867A (en) * 1991-10-11 1993-06-22 Intel Corporation Programmable logic array with internally generated precharge and evaluation timing
JPH05235747A (ja) * 1992-02-20 1993-09-10 Nec Corp ダイナミックｐｌａの低消費電力化方法

Also Published As

Publication number Publication date
US5559449A (en) 1996-09-24
JP3181009B2 (ja) 2001-07-03
DE69422794T2 (de) 2000-06-08
EP0669720A1 (de) 1995-08-30
JPH0856149A (ja) 1996-02-27
EP0669720B1 (de) 2000-01-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee