DE69406477D1 - Phasenregelkreis mit Abtast- und Halteschaltung - Google Patents

Phasenregelkreis mit Abtast- und Halteschaltung

Info

Publication number
DE69406477D1
DE69406477D1 DE69406477T DE69406477T DE69406477D1 DE 69406477 D1 DE69406477 D1 DE 69406477D1 DE 69406477 T DE69406477 T DE 69406477T DE 69406477 T DE69406477 T DE 69406477T DE 69406477 D1 DE69406477 D1 DE 69406477D1
Authority
DE
Germany
Prior art keywords
sample
locked loop
hold circuit
phase locked
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69406477T
Other languages
English (en)
Other versions
DE69406477T2 (de
Inventor
Noboru Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE69406477D1 publication Critical patent/DE69406477D1/de
Application granted granted Critical
Publication of DE69406477T2 publication Critical patent/DE69406477T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
DE69406477T 1993-03-01 1994-02-08 Phasenregelkreis mit Abtast- und Halteschaltung Expired - Fee Related DE69406477T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6246593 1993-03-01

Publications (2)

Publication Number Publication Date
DE69406477D1 true DE69406477D1 (de) 1997-12-04
DE69406477T2 DE69406477T2 (de) 1998-03-19

Family

ID=13200988

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69406477T Expired - Fee Related DE69406477T2 (de) 1993-03-01 1994-02-08 Phasenregelkreis mit Abtast- und Halteschaltung

Country Status (3)

Country Link
US (1) US5557648A (de)
EP (1) EP0614283B1 (de)
DE (1) DE69406477T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3499051B2 (ja) * 1995-06-22 2004-02-23 株式会社アドバンテスト タイミング信号発生回路
US5926515A (en) * 1995-12-26 1999-07-20 Samsung Electronics Co., Ltd. Phase locked loop for improving a phase locking time
CA2263221C (en) * 1996-08-13 2002-05-28 Masanori Kurita Pll circuit for digital display apparatus
GB2319934B (en) * 1996-11-27 2001-06-06 Sony Uk Ltd Digital signal processing
US6369626B1 (en) 1997-03-21 2002-04-09 Rambus Inc. Low pass filter for a delay locked loop circuit
JP2993559B2 (ja) 1997-03-31 1999-12-20 日本電気株式会社 位相同期回路
JP3072833B2 (ja) * 1997-05-23 2000-08-07 日本電気株式会社 ディジタルｐｌｌ回路
US6292522B1 (en) * 1997-11-13 2001-09-18 Lsi Logic Corporation Frequency decoder databank for phase-locked loop
US6115439A (en) * 1997-11-14 2000-09-05 Texas Instruments Incorporated Free running digital phase lock loop
US6111445A (en) 1998-01-30 2000-08-29 Rambus Inc. Phase interpolator with noise immunity
JP3834413B2 (ja) * 1998-02-18 2006-10-18 沖電気工業株式会社 位相制御回路および位相制御方法
JP3964528B2 (ja) * 1998-03-02 2007-08-22 富士通株式会社 シリアルバス高速化回路
KR100303315B1 (ko) * 1999-08-05 2001-11-01 윤종용 전송속도 무의존성의 광수신 방법 및 장치
US6678408B1 (en) * 1999-11-17 2004-01-13 Infocus Corporation Noise reduction through comparative histograms
KR100342567B1 (ko) * 1999-12-30 2002-07-04 윤종용 트랜스패런시를 확보한 광 교차-접속 장치
DE10005152A1 (de) * 2000-02-07 2001-08-09 Deutsche Telekom Mobil Verfahren zur Regeneration eines Taktsignals aus einem HDB3-codierten Eingangssignal und Taktregenerator zur Durchführung des Verfahrens
JP3765967B2 (ja) * 2000-06-30 2006-04-12 三菱電機株式会社 光送信装置およびこれに用いる光変調器のバイアス電圧制御方法
JP2002198810A (ja) * 2000-12-25 2002-07-12 Fujitsu Ltd 光受信機の入力断検出回路
JP2003008354A (ja) * 2001-06-26 2003-01-10 Mitsubishi Electric Corp Ａｍ復調器
DE10132403A1 (de) * 2001-07-09 2003-01-23 Alcatel Sa Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal
US7489757B2 (en) * 2003-05-01 2009-02-10 Mitsubishi Denki Kabushiki Kaisha Clock data recovery circuit
US7436921B1 (en) * 2004-11-05 2008-10-14 Rockwell Collins, Inc. Frequency sampling phase detector
JP5776657B2 (ja) 2012-09-18 2015-09-09 株式会社デンソー 受信回路
JP6036330B2 (ja) * 2013-01-22 2016-11-30 富士通株式会社 ジッタモニタ回路
US9258001B1 (en) 2013-09-03 2016-02-09 Cirrus Logic, Inc. Dual-input oscillator for redundant phase-locked loop (PLL) operation
JP6371096B2 (ja) * 2014-04-09 2018-08-08 ザインエレクトロニクス株式会社 受信装置
JP2019097080A (ja) * 2017-11-24 2019-06-20 富士通株式会社 信号再生回路、光モジュール及び信号再生方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573649A (en) 1969-01-08 1971-04-06 Us Navy Frequency-lock circuit
US4061979A (en) 1975-10-20 1977-12-06 Digital Communications Corporation Phase locked loop with pre-set and squelch
JPS58501519A (ja) * 1981-09-24 1983-09-08 キヤタピラ−　トラツクタ−　カンパニイ 信号調整回路
FR2597689B1 (fr) * 1986-04-22 1988-06-10 Trt Telecom Radio Electr Dispositif pour la recuperation de rythme convenant notamment pour un systeme de transmission d'informations utilisant dans un sens de transmission le principe dit d'a.m.r.t.
EP0355466A3 (de) * 1988-08-26 1990-06-20 Motorola, Inc. Integrierte Schaltung mit Taktgeberschaltung
US5036298A (en) * 1990-04-26 1991-07-30 Analog Devices, Inc. Clock recovery circuit without jitter peaking
US5028885A (en) * 1990-08-30 1991-07-02 Motorola, Inc. Phase-locked loop signal generation system with control maintenance
US5260979A (en) * 1991-05-28 1993-11-09 Codex Corp. Circuit and method of switching between redundant clocks for a phase lock loop

Also Published As

Publication number Publication date
EP0614283A1 (de) 1994-09-07
US5557648A (en) 1996-09-17
EP0614283B1 (de) 1997-10-29
DE69406477T2 (de) 1998-03-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee