DE69333806D1 - Verfahren und Gerät zur Prüfsequenzgenerierung - Google Patents

Verfahren und Gerät zur Prüfsequenzgenerierung

Info

Publication number
DE69333806D1
DE69333806D1 DE69333806T DE69333806T DE69333806D1 DE 69333806 D1 DE69333806 D1 DE 69333806D1 DE 69333806 T DE69333806 T DE 69333806T DE 69333806 T DE69333806 T DE 69333806T DE 69333806 D1 DE69333806 D1 DE 69333806D1
Authority
DE
Germany
Prior art keywords
test sequence
sequence generation
generation
test
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69333806T
Other languages
English (en)
Other versions
DE69333806T2 (de
Inventor
Toshinori Hosokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69333806D1 publication Critical patent/DE69333806D1/de
Application granted granted Critical
Publication of DE69333806T2 publication Critical patent/DE69333806T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318392—Generation of test inputs, e.g. test vectors, patterns or sequences for sequential circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE69333806T 1992-03-27 1993-03-26 Verfahren und Gerät zur Prüfsequenzgenerierung Expired - Fee Related DE69333806T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7075792 1992-03-27
JP7075792 1992-03-27

Publications (2)

Publication Number Publication Date
DE69333806D1 true DE69333806D1 (de) 2005-06-09
DE69333806T2 DE69333806T2 (de) 2005-10-06

Family

ID=13440705

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69333806T Expired - Fee Related DE69333806T2 (de) 1992-03-27 1993-03-26 Verfahren und Gerät zur Prüfsequenzgenerierung
DE69333510T Expired - Fee Related DE69333510T2 (de) 1992-03-27 1993-03-26 Verfahren und Gerät zur Prüfsequenzgenerierung

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE69333510T Expired - Fee Related DE69333510T2 (de) 1992-03-27 1993-03-26 Verfahren und Gerät zur Prüfsequenzgenerierung

Country Status (3)

Country Link
US (1) US5410552A (de)
EP (2) EP1132749B1 (de)
DE (2) DE69333806T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5602856A (en) * 1993-04-06 1997-02-11 Nippon Telegraph And Telephone Corporation Test pattern generation for logic circuits with reduced backtracking operations
US5566187A (en) * 1994-09-14 1996-10-15 Lucent Technologies Inc. Method for identifying untestable faults in logic circuits
US5559811A (en) * 1994-09-14 1996-09-24 Lucent Technologies Inc. Method for identifying untestable and redundant faults in sequential logic circuits.
JP3212228B2 (ja) * 1994-10-17 2001-09-25 富士通株式会社 試験プログラム作成装置における試験プログラム自動作成方法
US5862149A (en) * 1995-08-29 1999-01-19 Unisys Corporation Method of partitioning logic designs for automatic test pattern generation based on logical registers
JPH09145800A (ja) * 1995-11-17 1997-06-06 Nec Corp テストパターン生成方式
US6141630A (en) * 1997-08-07 2000-10-31 Verisity Design, Inc. System and method for automated design verification
US6865706B1 (en) * 2000-06-07 2005-03-08 Agilent Technologies, Inc. Apparatus and method for generating a set of test vectors using nonrandom filling
DE10144455A1 (de) * 2001-09-10 2003-04-03 Infineon Technologies Ag Verfahren zur Prüfung eines Abbilds einer elektrischen Schaltung
US6941497B2 (en) * 2002-01-15 2005-09-06 Agilent Technologies, Inc. N-squared algorithm for optimizing correlated events
US7685485B2 (en) * 2003-10-30 2010-03-23 Altera Corporation Functional failure analysis techniques for programmable integrated circuits
JP4418310B2 (ja) * 2004-06-29 2010-02-17 富士通株式会社 テストパターン生成方法およびテストパターン生成プログラム
DE102010062553A1 (de) * 2010-12-07 2012-06-14 Siemens Aktiengesellschaft Vorrichtung und Verfahren zum effizienten Durchführen von Systemtestläufen
JP2022187741A (ja) * 2021-06-08 2022-12-20 富士通株式会社 解析プログラム、解析方法及び解析装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1381413A (en) * 1972-06-21 1975-01-22 Ibm Methods of testing asynchronous sequential circuits
US4204633A (en) * 1978-11-20 1980-05-27 International Business Machines Corporation Logic chip test system with path oriented decision making test pattern generator
US4696006A (en) * 1984-11-26 1987-09-22 Nec Corporation Method of generating test patterns for logic network devices
US4937826A (en) * 1988-09-09 1990-06-26 Crosscheck Technology, Inc. Method and apparatus for sensing defects in integrated circuit elements
US4996689A (en) * 1989-02-01 1991-02-26 Vlsi Technology, Inc. Method of generating tests for a combinational logic circuit
JPH0587885A (ja) * 1991-09-30 1993-04-06 Matsushita Electric Ind Co Ltd 検査系列生成方法

Also Published As

Publication number Publication date
EP0562886B1 (de) 2004-05-12
EP1132749B1 (de) 2005-05-04
DE69333510D1 (de) 2004-06-17
DE69333806T2 (de) 2005-10-06
EP1132749A2 (de) 2001-09-12
US5410552A (en) 1995-04-25
DE69333510T2 (de) 2005-08-18
EP0562886A3 (en) 1996-11-06
EP0562886A2 (de) 1993-09-29
EP1132749A3 (de) 2002-02-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee