DE69326681D1 - Verfahren und Apparat zum Erzeugen von linearen Rückführungsschieberegistersequenzen - Google Patents

Verfahren und Apparat zum Erzeugen von linearen Rückführungsschieberegistersequenzen

Info

Publication number
DE69326681D1
DE69326681D1 DE69326681T DE69326681T DE69326681D1 DE 69326681 D1 DE69326681 D1 DE 69326681D1 DE 69326681 T DE69326681 T DE 69326681T DE 69326681 T DE69326681 T DE 69326681T DE 69326681 D1 DE69326681 D1 DE 69326681D1
Authority
DE
Germany
Prior art keywords
latch
exclusive
shift register
feedback shift
linear feedback
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69326681T
Other languages
English (en)
Other versions
DE69326681T2 (de
Inventor
Sean Francis Mullen
Jonathan Jedwab
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69326681D1 publication Critical patent/DE69326681D1/de
Application granted granted Critical
Publication of DE69326681T2 publication Critical patent/DE69326681T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31813—Test pattern generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318385—Random or pseudo-random test pattern
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/581—Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58—Indexing scheme relating to groups G06F7/58 - G06F7/588
    • G06F2207/583—Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs
DE69326681T 1993-04-06 1993-04-06 Verfahren und Apparat zum Erzeugen von linearen Rückführungsschieberegistersequenzen Expired - Fee Related DE69326681T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93302681A EP0620518B1 (de) 1993-04-06 1993-04-06 Verfahren und Apparat zum Erzeugen von linearen Rückführungsschieberegistersequenzen

Publications (2)

Publication Number Publication Date
DE69326681D1 true DE69326681D1 (de) 1999-11-11
DE69326681T2 DE69326681T2 (de) 2000-02-10

Family

ID=8214373

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69326681T Expired - Fee Related DE69326681T2 (de) 1993-04-06 1993-04-06 Verfahren und Apparat zum Erzeugen von linearen Rückführungsschieberegistersequenzen

Country Status (4)

Country Link
US (1) US5446683A (de)
EP (1) EP0620518B1 (de)
JP (1) JP3437635B2 (de)
DE (1) DE69326681T2 (de)

Families Citing this family (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0710908A3 (de) * 1994-11-01 1998-04-29 Motorola, Inc. Integrierter Koprozessor mit mehreren Übertragungsfunktionen
US5737360A (en) * 1995-06-19 1998-04-07 International Business Machines, Corp. System employing continuous-time dissipative pseudorandom dynamics for communications and measurement
US6697350B2 (en) 1995-06-30 2004-02-24 Interdigital Technology Corporation Adaptive vector correlator for spread-spectrum communications
US6885652B1 (en) 1995-06-30 2005-04-26 Interdigital Technology Corporation Code division multiple access (CDMA) communication system
US7929498B2 (en) 1995-06-30 2011-04-19 Interdigital Technology Corporation Adaptive forward power control and adaptive reverse power control for spread-spectrum communications
US6788662B2 (en) 1995-06-30 2004-09-07 Interdigital Technology Corporation Method for adaptive reverse power control for spread-spectrum communications
US6816473B2 (en) 1995-06-30 2004-11-09 Interdigital Technology Corporation Method for adaptive forward power control for spread-spectrum communications
ZA965340B (en) 1995-06-30 1997-01-27 Interdigital Tech Corp Code division multiple access (cdma) communication system
US7020111B2 (en) 1996-06-27 2006-03-28 Interdigital Technology Corporation System for using rapid acquisition spreading codes for spread-spectrum communications
US5745522A (en) * 1995-11-09 1998-04-28 General Instrument Corporation Of Delaware Randomizer for byte-wise scrambling of data
US5910907A (en) * 1997-02-20 1999-06-08 C.K. Chen Shift register based pseudorandom number generator
US6201870B1 (en) 1997-03-20 2001-03-13 Massachusetts Institue Of Technology Pseudorandom noise sequence generator
US6097889A (en) * 1997-06-23 2000-08-01 Motorola, Inc. Signal processing apparatus with stages in a signal path operating as LFSR of alternable type and method for processing signals
WO1999012316A2 (en) * 1997-09-04 1999-03-11 Silicon Image, Inc. Controllable delays in multiple synchronized signals for reduced electromagnetic interference at peak frequencies
JP3022439B2 (ja) * 1997-09-24 2000-03-21 日本電気株式会社 擬似乱数発生方法および装置
US20020051434A1 (en) * 1997-10-23 2002-05-02 Ozluturk Fatih M. Method for using rapid acquisition spreading codes for spread-spectrum communications
DE19821004C2 (de) 1998-05-11 2000-03-23 Ericsson Telefon Ab L M Sequenzgenerator
US6636553B1 (en) * 1998-12-29 2003-10-21 Texas Instruments Incorporated Pseudorandom noise generator for WCDMA
US6173009B1 (en) * 1998-12-29 2001-01-09 Texas Instruments Incorporated State calculation circuit for discrete linear state space model
US6115125A (en) * 1999-02-22 2000-09-05 Litton Systems Inc. Pseudorandom-bit-sequence modulated fiber-optic gyro
US6130755A (en) * 1999-02-22 2000-10-10 Litton Systems Inc. Fiber-optic gyro utilizing pseudorandom-bit-sequence light modulation
US6430586B1 (en) * 1999-06-08 2002-08-06 International Business Machines Corporation Controllable bit stream generator
US6590929B1 (en) 1999-06-08 2003-07-08 International Business Machines Corporation Method and system for run-time logic verification of operations in digital systems
US6457147B1 (en) 1999-06-08 2002-09-24 International Business Machines Corporation Method and system for run-time logic verification of operations in digital systems in response to a plurality of parameters
US6463448B1 (en) * 1999-09-30 2002-10-08 Agere Systems Guardian Corp. Linear intrasummed multiple-bit feedback shift register
US6560727B1 (en) * 1999-10-21 2003-05-06 Sandia Corporation Bit error rate tester using fast parallel generation of linear recurring sequences
IL132898A (en) * 1999-11-11 2009-09-01 Nds Ltd System for bitstream generation
US6724805B1 (en) 1999-11-15 2004-04-20 Massachusetts Institute Of Technology Nonlinear dynamic system for spread spectrum code generation and acquisition
US9664739B2 (en) 1999-11-23 2017-05-30 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
WO2001039254A2 (en) * 1999-11-23 2001-05-31 Mentor Graphics Corporation Continuous application and decompression of test patterns to a circuit-under-test
US6327687B1 (en) 1999-11-23 2001-12-04 Janusz Rajski Test pattern compression for an integrated circuit test environment
US8533547B2 (en) * 1999-11-23 2013-09-10 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US9134370B2 (en) 1999-11-23 2015-09-15 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6874109B1 (en) * 1999-11-23 2005-03-29 Janusz Rajski Phase shifter with reduced linear dependency
US6353842B1 (en) * 1999-11-23 2002-03-05 Janusz Rajski Method for synthesizing linear finite state machines
US6557129B1 (en) 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
US6684358B1 (en) 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
US7493540B1 (en) 1999-11-23 2009-02-17 Jansuz Rajski Continuous application and decompression of test patterns to a circuit-under-test
DE69939220D1 (de) * 1999-12-22 2008-09-11 Ericsson Telefon Ab L M Verfahren und elektrische Vorrichtung für die leistungsfähige Generierung von Mehrfachraten-Pseudozufallsfolgen
DE10085372T1 (de) * 1999-12-30 2003-06-18 Morphics Tech Inc Konfigurierbares Codegenerator-System für Spread-Spektrum-Anwendungen
US6665828B1 (en) * 2000-09-19 2003-12-16 International Business Machines Corporation Globally distributed scan blocks
US7072927B1 (en) * 2001-08-08 2006-07-04 Stephen Clark Purcell Method and apparatus for generating random numbers for use in a field programmable gate array
US7219112B2 (en) * 2001-11-20 2007-05-15 Ip-First, Llc Microprocessor with instruction translator for translating an instruction for storing random data bytes
US7149764B2 (en) * 2002-11-21 2006-12-12 Ip-First, Llc Random number generator bit string filter
US20060064448A1 (en) * 2001-11-20 2006-03-23 Ip-First, Llc. Continuous multi-buffering random number generator
US7136991B2 (en) * 2001-11-20 2006-11-14 Henry G Glenn Microprocessor including random number generator supporting operating system-independent multitasking operation
DE10216240A1 (de) 2002-04-12 2003-10-30 Infineon Technologies Ag Verfahren und Vorrichtung zur Berechnung eines iterierten Zustands einer rückgekoppelten Schieberegisteranordnung
US7209867B2 (en) * 2002-10-15 2007-04-24 Massachusetts Institute Of Technology Analog continuous time statistical processing
DE10250831B3 (de) * 2002-10-31 2004-06-17 Infineon Technologies Ag Vorrichtung und Verfahren zum Erzeugen einer pseudozufälligen Folge von Zahlen
US6765506B1 (en) * 2003-01-06 2004-07-20 Via Technologies Inc. Scrambler, de-scrambler, and related method
US7139785B2 (en) * 2003-02-11 2006-11-21 Ip-First, Llc Apparatus and method for reducing sequential bit correlation in a random number generator
DE102004010666B4 (de) * 2004-03-04 2006-02-02 Infineon Technologies Ag Schlüsselbitstromerzeugung
US7379955B1 (en) * 2004-03-16 2008-05-27 The United States Of America As Represented By The Director, National Security Agency Device for and method of generating pseudo-random sequence uniformly distributed over any range
TWI269222B (en) * 2004-12-29 2006-12-21 Univ Tsinghua Random number generating method and its equipment with a multiple polynomial
US8183980B2 (en) * 2005-08-31 2012-05-22 Assa Abloy Ab Device authentication using a unidirectional protocol
US20070168406A1 (en) * 2005-10-18 2007-07-19 Meyer David R Complementary linear feedback shift registers for generating advance timing masks
FR2899702A1 (fr) * 2006-04-10 2007-10-12 France Telecom Procede et dispositif pour engendrer une suite pseudo-aleatoire
JP5231079B2 (ja) * 2008-04-25 2013-07-10 ルネサスエレクトロニクス株式会社 疑似乱数発生器及びデータ通信装置
US20090327381A1 (en) * 2008-06-30 2009-12-31 Horizon Semiconductors Ltd. True random number generator
US8358783B2 (en) 2008-08-11 2013-01-22 Assa Abloy Ab Secure wiegand communications
JP5245635B2 (ja) * 2008-08-12 2013-07-24 沖電気工業株式会社 伝送路試験回路
JP5314693B2 (ja) 2008-09-12 2013-10-16 株式会社アドバンテスト 試験モジュールおよび試験方法
KR101037520B1 (ko) * 2008-12-02 2011-05-26 주식회사 팬택 광대역 무선통신시스템에서 스크램블링 코드 생성 방법 및 그 장치
KR100991957B1 (ko) * 2009-01-20 2010-11-04 주식회사 팬택 광대역 무선통신시스템에서의 스크램블링 코드 생성 장치 및 그 방법
WO2012016588A1 (en) * 2010-08-03 2012-02-09 Verigy (Singapore) Pte. Ltd. Bit sequence generator
US9128791B1 (en) * 2011-03-21 2015-09-08 Board Of Regents Of The University Of Texas System Generation of distinct pseudorandom number streams based on program context
US9157961B2 (en) * 2013-03-15 2015-10-13 Synopsys, Inc Two-level compression through selective reseeding
US9928036B2 (en) * 2015-09-25 2018-03-27 Intel Corporation Random number generator
US10452877B2 (en) 2016-12-16 2019-10-22 Assa Abloy Ab Methods to combine and auto-configure wiegand and RS485
US10673662B2 (en) * 2018-05-11 2020-06-02 Keysight Technologies, Inc. Methods and circuits for generating parallel pseudorandom binary sequences
US11774496B2 (en) * 2021-03-23 2023-10-03 Indian Institute Of Technology Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2049958B (en) * 1979-03-15 1983-11-30 Nippon Electric Co Integrated logic circuit adapted to performance tests
SU1248030A1 (ru) * 1984-12-30 1986-07-30 Харьковское Высшее Военное Командно-Инженерное Училище Ракетных Войск Им.Маршала Советского Союза Крылова Н.И. Генератор псевдослучайной последовательности
US4734921A (en) * 1986-11-25 1988-03-29 Grumman Aerospace Corporation Fully programmable linear feedback shift register
US5111416A (en) * 1989-02-20 1992-05-05 Clarion Co., Ltd. Pseudo random noise code generator for selectively generating a code or its mirror image from common data
JPH03214809A (ja) * 1990-01-19 1991-09-20 Nec Corp リニアフィードバック・シフトレジスタ
US5268949A (en) * 1990-03-28 1993-12-07 Ando Electric Co., Ltd. Circuit for generating M-sequence pseudo-random pattern

Also Published As

Publication number Publication date
US5446683A (en) 1995-08-29
EP0620518B1 (de) 1999-10-06
EP0620518A1 (de) 1994-10-19
DE69326681T2 (de) 2000-02-10
JPH0772222A (ja) 1995-03-17
JP3437635B2 (ja) 2003-08-18

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee