DE69323513D1 - Planaxer Kontakt mit einer Lücke - Google Patents

Planaxer Kontakt mit einer Lücke

Info

Publication number
DE69323513D1
DE69323513D1 DE69323513T DE69323513T DE69323513D1 DE 69323513 D1 DE69323513 D1 DE 69323513D1 DE 69323513 T DE69323513 T DE 69323513T DE 69323513 T DE69323513 T DE 69323513T DE 69323513 D1 DE69323513 D1 DE 69323513D1
Authority
DE
Germany
Prior art keywords
planax
gap
contact
planax contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69323513T
Other languages
English (en)
Other versions
DE69323513T2 (de
Inventor
Fusen E Chen
Girish Anant Dixit
Robert O Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25442920&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69323513(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69323513D1 publication Critical patent/DE69323513D1/de
Application granted granted Critical
Publication of DE69323513T2 publication Critical patent/DE69323513T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69323513T 1992-07-27 1993-07-08 Planaxer Kontakt mit einer Lücke Expired - Fee Related DE69323513T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US91994892A 1992-07-27 1992-07-27

Publications (2)

Publication Number Publication Date
DE69323513D1 true DE69323513D1 (de) 1999-03-25
DE69323513T2 DE69323513T2 (de) 1999-08-12

Family

ID=25442920

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69323513T Expired - Fee Related DE69323513T2 (de) 1992-07-27 1993-07-08 Planaxer Kontakt mit einer Lücke

Country Status (4)

Country Link
US (2) US5571752A (de)
EP (1) EP0583876B1 (de)
JP (1) JPH06204225A (de)
DE (1) DE69323513T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563089A (en) * 1994-07-20 1996-10-08 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
US6348708B1 (en) * 1995-04-10 2002-02-19 Lg Semicon Co., Ltd. Semiconductor device utilizing a rugged tungsten film
JPH10125865A (ja) * 1996-10-15 1998-05-15 Fujitsu Ltd 半導体装置、半導体記憶装置、およびその製造方法
EP0867940A3 (de) 1997-03-27 1999-10-13 Applied Materials, Inc. Eine Unterschicht für eine Aluminiumverbindung
US5882399A (en) * 1997-08-23 1999-03-16 Applied Materials, Inc. Method of forming a barrier layer which enables a consistently highly oriented crystalline structure in a metallic interconnect
US6887353B1 (en) * 1997-12-19 2005-05-03 Applied Materials, Inc. Tailored barrier layer which provides improved copper interconnect electromigration resistance
US7253109B2 (en) 1997-11-26 2007-08-07 Applied Materials, Inc. Method of depositing a tantalum nitride/tantalum diffusion barrier layer system
US6320261B1 (en) * 1998-04-21 2001-11-20 Micron Technology, Inc. High aspect ratio metallization structures for shallow junction devices, and methods of forming the same
JP3367427B2 (ja) * 1998-08-11 2003-01-14 株式会社高岳製作所 単相三線式変圧器
US6255192B1 (en) * 1998-09-29 2001-07-03 Conexant Systems, Inc. Methods for barrier layer formation
US6359314B1 (en) 1999-09-02 2002-03-19 Lsi Logic Corporation Swapped drain structures for electrostatic discharge protection
KR100478483B1 (ko) * 2002-10-02 2005-03-28 동부아남반도체 주식회사 반도체 소자의 제조 방법

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592352A (ja) * 1982-06-28 1984-01-07 Toshiba Corp 半導体装置の製造方法
JPS60186038A (ja) * 1984-03-05 1985-09-21 Fujitsu Ltd 半導体装置
US4920071A (en) * 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
US4796081A (en) * 1986-05-02 1989-01-03 Advanced Micro Devices, Inc. Low resistance metal contact for silicon devices
US4970573A (en) * 1986-07-01 1990-11-13 Harris Corporation Self-planarized gold interconnect layer
US4884123A (en) * 1987-02-19 1989-11-28 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
US4960732A (en) * 1987-02-19 1990-10-02 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
JPH01108746A (ja) * 1987-10-21 1989-04-26 Toshiba Corp 半導体装置の製造方法
JP2776826B2 (ja) * 1988-04-15 1998-07-16 株式会社日立製作所 半導体装置およびその製造方法
JPH0250354A (ja) * 1988-08-11 1990-02-20 Nec Corp 外部記憶装置
US5104826A (en) * 1989-02-02 1992-04-14 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor integrated circuit device using an electrode wiring structure
JPH02250354A (ja) * 1989-03-24 1990-10-08 Toshiba Corp 半導体装置の製造方法
EP0397131B1 (de) * 1989-05-09 1995-04-05 Fujitsu Limited Verfahren zur Herstellung von Kontakten in Halbleiterbauelementen
DE69031903T2 (de) * 1989-11-30 1998-04-16 Sgs Thomson Microelectronics Verfahren zum Herstellen von Zwischenschicht-Kontakten
JPH03187244A (ja) * 1989-12-15 1991-08-15 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH03201482A (ja) * 1989-12-28 1991-09-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5094981A (en) * 1990-04-17 1992-03-10 North American Philips Corporation, Signetics Div. Technique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier material above 550° C.
JPH05234935A (ja) * 1992-02-20 1993-09-10 Matsushita Electron Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
US5578872A (en) 1996-11-26
EP0583876A2 (de) 1994-02-23
EP0583876B1 (de) 1999-02-17
US5571752A (en) 1996-11-05
EP0583876A3 (en) 1994-05-25
JPH06204225A (ja) 1994-07-22
DE69323513T2 (de) 1999-08-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee