DE69317963D1 - Integrierte Speicherschaltung mit Ausgangsvorladung - Google Patents

Integrierte Speicherschaltung mit Ausgangsvorladung

Info

Publication number
DE69317963D1
DE69317963D1 DE69317963T DE69317963T DE69317963D1 DE 69317963 D1 DE69317963 D1 DE 69317963D1 DE 69317963 T DE69317963 T DE 69317963T DE 69317963 T DE69317963 T DE 69317963T DE 69317963 D1 DE69317963 D1 DE 69317963D1
Authority
DE
Germany
Prior art keywords
charging
memory circuit
integrated memory
output pre
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69317963T
Other languages
English (en)
Other versions
DE69317963T2 (de
Inventor
Jean-Marie Gaultier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Publication of DE69317963D1 publication Critical patent/DE69317963D1/de
Application granted granted Critical
Publication of DE69317963T2 publication Critical patent/DE69317963T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
DE69317963T 1992-07-24 1993-07-23 Integrierte Speicherschaltung mit Ausgangsvorladung Expired - Fee Related DE69317963T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9209197A FR2694121B1 (fr) 1992-07-24 1992-07-24 Memoire en circuit integre avec prechaarge prealable en sortie.

Publications (2)

Publication Number Publication Date
DE69317963D1 true DE69317963D1 (de) 1998-05-20
DE69317963T2 DE69317963T2 (de) 1998-08-06

Family

ID=9432264

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69317963T Expired - Fee Related DE69317963T2 (de) 1992-07-24 1993-07-23 Integrierte Speicherschaltung mit Ausgangsvorladung

Country Status (5)

Country Link
US (1) US5377149A (de)
EP (1) EP0585153B1 (de)
JP (1) JPH06187792A (de)
DE (1) DE69317963T2 (de)
FR (1) FR2694121B1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5831908A (en) * 1994-07-29 1998-11-03 Nkk Corporation Data output circuit, intermediate potential setting circuit, and semiconductor integrated circuit
US5698994A (en) * 1994-07-29 1997-12-16 Nkk Corporation Data output circuit, intermediate potential setting circuit, and semiconductor integrated circuit
US6107838A (en) * 1995-02-01 2000-08-22 Honeywell International, Inc. Simultaneous two-way communication system using a single communication port
US5654648A (en) * 1995-03-06 1997-08-05 Alliance Semiconductor Corporation Output buffer circuit with low power pre-output drive
US5557581A (en) * 1995-04-10 1996-09-17 Sun Microsystems, Inc. Logic and memory circuit with reduced input-to-output signal propagation delay
US5703501A (en) * 1995-11-27 1997-12-30 Advanced Micro Devices, Inc. Apparatus and method for precharging a bus to an intermediate level
KR100429861B1 (ko) * 1997-06-23 2004-07-19 삼성전자주식회사 온 스크린 디스플레이 시스템의 정적 메모리를 위한 프리 차지 신호 발생장치
US5999469A (en) * 1998-03-04 1999-12-07 Lsi Logic Corporation Sense time reduction using midlevel precharge
US6281719B1 (en) 1999-10-29 2001-08-28 Macronix International Co., Ltd. Output pad precharge circuit for semiconductor devices
US6559678B1 (en) * 2001-12-24 2003-05-06 Nanoamp Solutions, Inc. Node predisposition circuit
JP4088954B2 (ja) * 2002-03-04 2008-05-21 日本電気株式会社 半導体記憶装置の読み出し回路
KR101858470B1 (ko) * 2011-12-21 2018-05-17 에스케이하이닉스 주식회사 반도체 장치
TWI511456B (zh) * 2014-01-15 2015-12-01 Elite Semiconductor Esmt 輸入緩衝器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63112893A (ja) * 1986-10-28 1988-05-17 Mitsubishi Electric Corp 半導体集積回路
JP2569538B2 (ja) * 1987-03-17 1997-01-08 ソニー株式会社 メモリ装置
JPH0817037B2 (ja) * 1987-12-03 1996-02-21 松下電子工業株式会社 スタティックｒａｍの出力回路
US5204838A (en) * 1988-10-28 1993-04-20 Fuji Xerox Co., Ltd. High speed readout circuit
KR910005602B1 (ko) * 1989-06-15 1991-07-31 삼성전자 주식회사 어드레스 변환 검출에 따른 출력버퍼의 프리챠아지 제어방법
JP2900559B2 (ja) * 1990-08-09 1999-06-02 日本電気株式会社 データ出力回路

Also Published As

Publication number Publication date
EP0585153A1 (de) 1994-03-02
EP0585153B1 (de) 1998-04-15
US5377149A (en) 1994-12-27
JPH06187792A (ja) 1994-07-08
FR2694121A1 (fr) 1994-01-28
FR2694121B1 (fr) 1995-09-22
DE69317963T2 (de) 1998-08-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee