DE69317240D1 - Eingangs-Verstärkerschaltung - Google Patents

Eingangs-Verstärkerschaltung

Info

Publication number
DE69317240D1
DE69317240D1 DE69317240T DE69317240T DE69317240D1 DE 69317240 D1 DE69317240 D1 DE 69317240D1 DE 69317240 T DE69317240 T DE 69317240T DE 69317240 T DE69317240 T DE 69317240T DE 69317240 D1 DE69317240 D1 DE 69317240D1
Authority
DE
Germany
Prior art keywords
amplifier circuit
input amplifier
input
circuit
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69317240T
Other languages
English (en)
Other versions
DE69317240T2 (de
Inventor
Susumu Uriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69317240D1 publication Critical patent/DE69317240D1/de
Application granted granted Critical
Publication of DE69317240T2 publication Critical patent/DE69317240T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/303—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
DE69317240T 1992-12-28 1993-12-24 Eingangs-Verstärkerschaltung Expired - Fee Related DE69317240T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4359826A JP2581387B2 (ja) 1992-12-28 1992-12-28 入力増幅回路

Publications (2)

Publication Number Publication Date
DE69317240D1 true DE69317240D1 (de) 1998-04-09
DE69317240T2 DE69317240T2 (de) 1998-06-25

Family

ID=18466496

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69317240T Expired - Fee Related DE69317240T2 (de) 1992-12-28 1993-12-24 Eingangs-Verstärkerschaltung

Country Status (5)

Country Link
US (1) US5502417A (de)
EP (1) EP0605233B1 (de)
JP (1) JP2581387B2 (de)
CA (1) CA2112203C (de)
DE (1) DE69317240T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147541A (en) * 1996-10-02 2000-11-14 Endress + Hauser Gmbh + Co. Monolithic MOS-SC circuit
JP2001195383A (ja) * 2000-01-11 2001-07-19 Mitsubishi Electric Corp マイクロコンピュータ
KR100616711B1 (ko) * 2003-06-20 2006-08-28 엘지.필립스 엘시디 주식회사 액정표시장치의 구동회로
JP4167952B2 (ja) * 2003-07-24 2008-10-22 セイコーエプソン株式会社 表示ドライバ、電気光学装置及び駆動方法
JP4625732B2 (ja) * 2005-07-25 2011-02-02 富士通セミコンダクター株式会社 入力増幅回路
KR100799132B1 (ko) * 2006-06-29 2008-01-29 주식회사 하이닉스반도체 초기값변경이 가능한 모드레지스터셋회로.
US8937468B2 (en) 2012-08-13 2015-01-20 Northrop Grumman Systems Corporation Power supply systems and methods

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3812384A (en) * 1973-05-17 1974-05-21 Rca Corp Set-reset flip-flop
JPS59134918A (ja) * 1983-01-24 1984-08-02 Toshiba Corp ラツチ回路
JPS59156007A (ja) * 1983-02-25 1984-09-05 Hitachi Ltd 増幅回路
JPS60142610A (ja) * 1983-12-28 1985-07-27 Fujitsu Ltd コンパレ−タ回路
JPS6226910A (ja) * 1985-07-26 1987-02-04 Nec Corp 入力アンプ回路
JPS62145906A (ja) * 1985-12-20 1987-06-30 Nec Corp 増幅回路
JPH063679B2 (ja) * 1987-10-30 1994-01-12 株式会社東芝 半導体装置の制御回路
JPH0636482B2 (ja) * 1988-08-30 1994-05-11 日本電気株式会社 入力アンプ回路
US4963769A (en) * 1989-05-08 1990-10-16 Cypress Semiconductor Circuit for selective power-down of unused circuitry
US5115150A (en) * 1990-11-19 1992-05-19 Hewlett-Packard Co. Low power CMOS bus receiver with small setup time
US5311070A (en) * 1992-06-26 1994-05-10 Harris Corporation Seu-immune latch for gate array, standard cell, and other asic applications

Also Published As

Publication number Publication date
JP2581387B2 (ja) 1997-02-12
CA2112203C (en) 1997-09-09
EP0605233A3 (en) 1994-08-24
EP0605233A2 (de) 1994-07-06
US5502417A (en) 1996-03-26
DE69317240T2 (de) 1998-06-25
JPH06204818A (ja) 1994-07-22
CA2112203A1 (en) 1994-06-29
EP0605233B1 (de) 1998-03-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee