DE69232168T2 - CMOS-Logikschaltung - Google Patents

CMOS-Logikschaltung

Info

Publication number
DE69232168T2
DE69232168T2 DE69232168T DE69232168T DE69232168T2 DE 69232168 T2 DE69232168 T2 DE 69232168T2 DE 69232168 T DE69232168 T DE 69232168T DE 69232168 T DE69232168 T DE 69232168T DE 69232168 T2 DE69232168 T2 DE 69232168T2
Authority
DE
Germany
Prior art keywords
logic circuit
cmos logic
cmos
circuit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69232168T
Other languages
English (en)
Other versions
DE69232168D1 (de
Inventor
Antonio Imbruglia
Giovanni Benenati
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Original Assignee
CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno filed Critical CORIMME Consorzio per Ricerca Sulla Microelettronica nel Mezzogiorno
Publication of DE69232168D1 publication Critical patent/DE69232168D1/de
Application granted granted Critical
Publication of DE69232168T2 publication Critical patent/DE69232168T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
DE69232168T 1992-05-27 1992-05-27 CMOS-Logikschaltung Expired - Lifetime DE69232168T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92830269A EP0575686B1 (de) 1992-05-27 1992-05-27 CMOS-Logikschaltung

Publications (2)

Publication Number Publication Date
DE69232168D1 DE69232168D1 (de) 2001-12-06
DE69232168T2 true DE69232168T2 (de) 2002-07-18

Family

ID=8212114

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69232168T Expired - Lifetime DE69232168T2 (de) 1992-05-27 1992-05-27 CMOS-Logikschaltung

Country Status (4)

Country Link
US (1) US5440242A (de)
EP (1) EP0575686B1 (de)
JP (1) JPH06326594A (de)
DE (1) DE69232168T2 (de)

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4032795A (en) * 1976-04-14 1977-06-28 Solitron Devices, Inc. Input buffer
NL8105919A (nl) * 1981-12-31 1983-07-18 Philips Nv Dynamische versterkerschakeling.
JPS58117729A (ja) * 1981-12-31 1983-07-13 Fujitsu Ltd Ｍｏｓトランジスタ回路
GB2113934B (en) * 1982-01-26 1986-05-14 Standard Telephones Cables Ltd Determining switching threshold in cmos circuits
US4472647A (en) * 1982-08-20 1984-09-18 Motorola, Inc. Circuit for interfacing with both TTL and CMOS voltage levels
JPS5964916A (ja) * 1982-10-06 1984-04-13 Toshiba Corp 閾値可変論理回路
US4794282A (en) * 1985-03-21 1988-12-27 Brooktree Corporation TTL to CMOS voltage level translator
US4649294A (en) * 1986-01-13 1987-03-10 Motorola, Inc. BIMOS logic gate
JPH01194608A (ja) * 1988-01-29 1989-08-04 Hitachi Ltd 半導体論理回路
JPH01204520A (ja) * 1988-02-10 1989-08-17 Mitsubishi Electric Corp レベル変換回路
JPH0286323A (ja) * 1988-09-22 1990-03-27 Fujitsu Ltd 半導体論理装置
US5264744A (en) * 1989-11-21 1993-11-23 Hitachi, Ltd. Complementary signal transmission circuit with impedance matching circuitry
JP2558904B2 (ja) * 1990-01-19 1996-11-27 株式会社東芝 半導体集積回路
EP0542321A3 (en) * 1991-09-23 1993-06-09 Schlumberger Technologies, Inc. Method and circuit for controlling voltage reflections on transmission lines
US5227677A (en) * 1992-06-10 1993-07-13 International Business Machines Corporation Zero power transmission line terminator

Also Published As

Publication number Publication date
JPH06326594A (ja) 1994-11-25
EP0575686B1 (de) 2001-10-31
DE69232168D1 (de) 2001-12-06
EP0575686A1 (de) 1993-12-29
US5440242A (en) 1995-08-08

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R071 Expiry of right

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