DE69223660D1 - Fehlersichere Logikschaltung - Google Patents

Fehlersichere Logikschaltung

Info

Publication number
DE69223660D1
DE69223660D1 DE69223660T DE69223660T DE69223660D1 DE 69223660 D1 DE69223660 D1 DE 69223660D1 DE 69223660 T DE69223660 T DE 69223660T DE 69223660 T DE69223660 T DE 69223660T DE 69223660 D1 DE69223660 D1 DE 69223660D1
Authority
DE
Germany
Prior art keywords
fail
logic circuit
safe logic
safe
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69223660T
Other languages
English (en)
Other versions
DE69223660T2 (de
Inventor
Makoto Nomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE69223660D1 publication Critical patent/DE69223660D1/de
Application granted granted Critical
Publication of DE69223660T2 publication Critical patent/DE69223660T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits

Landscapes

  • Logic Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
DE1992623660 1991-02-05 1992-01-27 Fehlersichere Logikschaltung Expired - Lifetime DE69223660T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01417291A JP3277510B2 (ja) 1991-02-05 1991-02-05 フェイルセーフ論理回路

Publications (2)

Publication Number Publication Date
DE69223660D1 true DE69223660D1 (de) 1998-02-05
DE69223660T2 DE69223660T2 (de) 1998-07-16

Family

ID=11853726

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1992623660 Expired - Lifetime DE69223660T2 (de) 1991-02-05 1992-01-27 Fehlersichere Logikschaltung

Country Status (3)

Country Link
EP (1) EP0498248B1 (de)
JP (1) JP3277510B2 (de)
DE (1) DE69223660T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100573311B1 (ko) * 2004-02-02 2006-04-24 학교법인 한양학원 비반전 출력을 가지는 2단 플립플롭
WO2015075783A1 (ja) * 2013-11-20 2015-05-28 株式会社日立製作所 論理集積回路及びこれを用いた論理回路，比較器，高信頼性システム

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673429A (en) * 1970-10-19 1972-06-27 Westinghouse Electric Corp Pseudo-and gate having failsafe qualities
US4797575A (en) * 1986-12-05 1989-01-10 Western Digital Corporation Flip-flop with identical propagation delay in clock pass through mode and in normal operation

Also Published As

Publication number Publication date
EP0498248A1 (de) 1992-08-12
EP0498248B1 (de) 1997-12-29
JP3277510B2 (ja) 2002-04-22
JPH04248712A (ja) 1992-09-04
DE69223660T2 (de) 1998-07-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition