DE69319361D1 - Logische Schaltung - Google Patents

Logische Schaltung

Info

Publication number
DE69319361D1
DE69319361D1 DE69319361T DE69319361T DE69319361D1 DE 69319361 D1 DE69319361 D1 DE 69319361D1 DE 69319361 T DE69319361 T DE 69319361T DE 69319361 T DE69319361 T DE 69319361T DE 69319361 D1 DE69319361 D1 DE 69319361D1
Authority
DE
Germany
Prior art keywords
logical circuit
logical
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69319361T
Other languages
English (en)
Other versions
DE69319361T2 (de
Inventor
Kazuo Nakazato
Julian D White
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Europe Ltd
Original Assignee
Hitachi Europe Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Europe Ltd filed Critical Hitachi Europe Ltd
Application granted granted Critical
Publication of DE69319361D1 publication Critical patent/DE69319361D1/de
Publication of DE69319361T2 publication Critical patent/DE69319361T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/501Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/502Half adders; Full adders consisting of two cascaded half adders
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02Structural aspects of erasable programmable read-only memories
    • G11C2216/08Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Nanotechnology (AREA)
  • General Engineering & Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Optimization (AREA)
  • Logic Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
DE1993619361 1992-03-25 1993-03-16 Logische Schaltung Expired - Fee Related DE69319361T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB929206812A GB9206812D0 (en) 1992-03-25 1992-03-25 Logic device

Publications (2)

Publication Number Publication Date
DE69319361D1 true DE69319361D1 (de) 1998-08-06
DE69319361T2 DE69319361T2 (de) 1999-04-01

Family

ID=10713037

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1993619361 Expired - Fee Related DE69319361T2 (de) 1992-03-25 1993-03-16 Logische Schaltung

Country Status (4)

Country Link
EP (1) EP0562751B1 (de)
JP (1) JP3462524B2 (de)
DE (1) DE69319361T2 (de)
GB (1) GB9206812D0 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9415718D0 (en) 1994-08-03 1994-09-21 Hitachi Europ Ltd Conduction control device
GB2328096B (en) * 1997-08-01 2001-10-17 Simon Charles Benjamin Cellular circuitry
DE19738115C1 (de) * 1997-09-01 1999-03-18 Siemens Ag Schaltungsanordnung mit Einzelelektron-Bauelementen, Verfahren zu deren Betrieb und Anwendung des Verfahrens zur Addition von Binärzahlen
GB9724642D0 (en) 1997-11-21 1998-01-21 British Tech Group Single electron devices
DE19820050C1 (de) 1998-05-05 1999-03-25 Siemens Ag Schaltungsanordnung mit Einzelelektron-Bauelementen und Verfahren zu deren Betrieb
GB9925213D0 (en) * 1999-10-25 1999-12-22 Univ Cambridge Tech Magnetic logic elements
TWI557749B (zh) * 2013-06-13 2016-11-11 中村維男 直接轉移跨步記憶體及使用該記憶體之電腦系統

Also Published As

Publication number Publication date
GB9206812D0 (en) 1992-05-13
JPH06224411A (ja) 1994-08-12
DE69319361T2 (de) 1999-04-01
EP0562751A3 (en) 1994-05-18
EP0562751A2 (de) 1993-09-29
EP0562751B1 (de) 1998-07-01
JP3462524B2 (ja) 2003-11-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee