DE69325476T2 - Abrundungsschaltung - Google Patents

Abrundungsschaltung

Info

Publication number
DE69325476T2
DE69325476T2 DE69325476T DE69325476T DE69325476T2 DE 69325476 T2 DE69325476 T2 DE 69325476T2 DE 69325476 T DE69325476 T DE 69325476T DE 69325476 T DE69325476 T DE 69325476T DE 69325476 T2 DE69325476 T2 DE 69325476T2
Authority
DE
Germany
Prior art keywords
rounding circuit
rounding
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69325476T
Other languages
English (en)
Other versions
DE69325476D1 (de
Inventor
Yoshitaka Toriumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69325476D1 publication Critical patent/DE69325476D1/de
Publication of DE69325476T2 publication Critical patent/DE69325476T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49963—Rounding to nearest
DE69325476T 1992-03-23 1993-03-22 Abrundungsschaltung Expired - Fee Related DE69325476T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4064425A JPH05265709A (ja) 1992-03-23 1992-03-23 丸め演算回路

Publications (2)

Publication Number Publication Date
DE69325476D1 DE69325476D1 (de) 1999-08-05
DE69325476T2 true DE69325476T2 (de) 2000-03-02

Family

ID=13257918

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69325476T Expired - Fee Related DE69325476T2 (de) 1992-03-23 1993-03-22 Abrundungsschaltung

Country Status (4)

Country Link
US (1) US5317530A (de)
EP (1) EP0562513B1 (de)
JP (1) JPH05265709A (de)
DE (1) DE69325476T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06348455A (ja) * 1993-06-14 1994-12-22 Matsushita Electric Ind Co Ltd 乗算における丸め込み方法及び乗算回路
US5729481A (en) * 1995-03-31 1998-03-17 International Business Machines Corporation Method and system of rounding for quadratically converging division or square root
US5633689A (en) * 1995-12-29 1997-05-27 Thomson Consumer Electronics, Inc. Apparatus for separating a digital composite video signal into components
US5696710A (en) * 1995-12-29 1997-12-09 Thomson Consumer Electronics, Inc. Apparatus for symmetrically reducing N least significant bits of an M-bit digital signal
JPH10133856A (ja) * 1996-10-31 1998-05-22 Nec Corp 丸め機能付き乗算方法及び乗算器
US6058215A (en) * 1997-04-30 2000-05-02 Ricoh Company, Ltd. Reversible DCT for lossless-lossy compression
US7840627B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Digital signal processing circuit having input register blocks
US7467175B2 (en) * 2003-12-29 2008-12-16 Xilinx, Inc. Programmable logic device with pipelined DSP slices
US7844653B2 (en) * 2003-12-29 2010-11-30 Xilinx, Inc. Digital signal processing circuit having a pre-adder circuit
US7480690B2 (en) * 2003-12-29 2009-01-20 Xilinx, Inc. Arithmetic circuit with multiplexed addend inputs
US8495122B2 (en) * 2003-12-29 2013-07-23 Xilinx, Inc. Programmable device with dynamic DSP architecture
US7853634B2 (en) * 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a SIMD circuit
US7860915B2 (en) * 2003-12-29 2010-12-28 Xilinx, Inc. Digital signal processing circuit having a pattern circuit for determining termination conditions
US7567997B2 (en) * 2003-12-29 2009-07-28 Xilinx, Inc. Applications of cascading DSP slices
US7882165B2 (en) * 2003-12-29 2011-02-01 Xilinx, Inc. Digital signal processing element having an arithmetic logic unit
US7865542B2 (en) * 2003-12-29 2011-01-04 Xilinx, Inc. Digital signal processing block having a wide multiplexer
US7853636B2 (en) 2003-12-29 2010-12-14 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit for convergent rounding
US7853632B2 (en) * 2003-12-29 2010-12-14 Xilinx, Inc. Architectural floorplan for a digital signal processing circuit
US7849119B2 (en) * 2003-12-29 2010-12-07 Xilinx, Inc. Digital signal processing circuit having a pattern detector circuit
US7840630B2 (en) * 2003-12-29 2010-11-23 Xilinx, Inc. Arithmetic logic unit circuit
US7870182B2 (en) * 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US7472155B2 (en) * 2003-12-29 2008-12-30 Xilinx, Inc. Programmable logic device with cascading DSP slices
US20080028014A1 (en) * 2006-07-26 2008-01-31 Hilt Jason W N-BIT 2's COMPLEMENT SYMMETRIC ROUNDING METHOD AND LOGIC FOR IMPLEMENTING THE SAME
US8443029B2 (en) * 2007-03-01 2013-05-14 International Business Machines Corporation Round for reround mode in a decimal floating point instruction
US8543635B2 (en) * 2009-01-27 2013-09-24 Xilinx, Inc. Digital signal processing block with preadder stage
US8479133B2 (en) * 2009-01-27 2013-07-02 Xilinx, Inc. Method of and circuit for implementing a filter in an integrated circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3891837A (en) * 1972-07-03 1975-06-24 Drew E Sunstein Digital linearity and bias error compensating by adding an extra bit
US4589084A (en) * 1983-05-16 1986-05-13 Rca Corporation Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals
JPS61237133A (ja) * 1985-04-15 1986-10-22 Nec Corp 演算回路
JPH0484318A (ja) * 1990-07-27 1992-03-17 Nec Corp 丸め演算回路
JP3199371B2 (ja) * 1990-07-30 2001-08-20 松下電器産業株式会社 丸め装置

Also Published As

Publication number Publication date
EP0562513A3 (en) 1993-10-20
EP0562513B1 (de) 1999-06-30
EP0562513A2 (de) 1993-09-29
JPH05265709A (ja) 1993-10-15
DE69325476D1 (de) 1999-08-05
US5317530A (en) 1994-05-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee