DE69230118T2 - Prozessor mit hierarchischer Struktur - Google Patents
Prozessor mit hierarchischer StrukturInfo
- Publication number
- DE69230118T2 DE69230118T2 DE69230118T DE69230118T DE69230118T2 DE 69230118 T2 DE69230118 T2 DE 69230118T2 DE 69230118 T DE69230118 T DE 69230118T DE 69230118 T DE69230118 T DE 69230118T DE 69230118 T2 DE69230118 T2 DE 69230118T2
- Authority
- DE
- Germany
- Prior art keywords
- processor
- hierarchical structure
- hierarchical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3162631A JP2884831B2 (ja) | 1991-07-03 | 1991-07-03 | 処理装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69230118D1 DE69230118D1 (de) | 1999-11-18 |
DE69230118T2 true DE69230118T2 (de) | 2000-02-03 |
Family
ID=15758283
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69230118T Expired - Fee Related DE69230118T2 (de) | 1991-07-03 | 1992-07-01 | Prozessor mit hierarchischer Struktur |
Country Status (4)
Country | Link |
---|---|
US (1) | US5530889A (de) |
EP (1) | EP0521486B1 (de) |
JP (1) | JP2884831B2 (de) |
DE (1) | DE69230118T2 (de) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2137488C (en) * | 1994-02-18 | 1998-09-29 | Richard I. Baum | Coexecuting method and means for performing parallel processing in conventional types of data processing systems |
US5752071A (en) * | 1995-07-17 | 1998-05-12 | Intel Corporation | Function coprocessor |
US5987602A (en) * | 1997-05-06 | 1999-11-16 | Microsoft Corporation | Parameterless language in a machine for implementation thereof |
US6496926B1 (en) * | 1997-05-06 | 2002-12-17 | Microsoft Corporation | Computer-implemented paramaterless language with exception handler |
US6216218B1 (en) | 1997-11-03 | 2001-04-10 | Donald L. Sollars | Processor having a datapath and control logic constituted with basis execution blocks |
US6016539A (en) * | 1997-11-03 | 2000-01-18 | Teragen Corporation | Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations |
US6237083B1 (en) | 1998-02-13 | 2001-05-22 | Advanced Micro Devices, Inc. | Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instruction sequence |
US6317820B1 (en) * | 1998-06-05 | 2001-11-13 | Texas Instruments Incorporated | Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism |
WO2001077818A2 (en) * | 2000-04-05 | 2001-10-18 | Infineon Technologies North America Corp. | Method for predicting the instruction execution latency of a de-coupled configurable co-processor |
JP4699685B2 (ja) | 2003-08-21 | 2011-06-15 | パナソニック株式会社 | 信号処理装置及びそれを用いた電子機器 |
EP2278452A1 (de) * | 2009-07-15 | 2011-01-26 | Nxp B.V. | Koprozessorprogrammierung |
JP2010055629A (ja) * | 2009-11-30 | 2010-03-11 | Panasonic Corp | 画像音声信号処理装置及びそれを用いた電子機器 |
DE102018201417A1 (de) | 2018-01-30 | 2019-08-01 | Volkswagen Aktiengesellschaft | Verfahren zum Bereitstellen verifizierter Informationen über ein Verkehrszeichen, Verkehrszeichenanlage sowie Verfahren für ein Navigationssystem zur Verifikation eines Verkehrszeichens |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4750110A (en) * | 1983-04-18 | 1988-06-07 | Motorola, Inc. | Method and apparatus for executing an instruction contingent upon a condition present in another data processor |
DE3486465D1 (de) * | 1983-04-18 | 1998-04-02 | Motorola Inc | Verfahren und Vorrichtung zum Koordinieren einer Instruktionsausführung durch eine Zusatzdatenverarbeitungseinheit |
US4914578A (en) * | 1983-04-18 | 1990-04-03 | Motorola, Inc. | Method and apparatus for interrupting a coprocessor |
JPS62214464A (ja) * | 1986-03-17 | 1987-09-21 | Hitachi Ltd | データ処理システム |
JPH0619760B2 (ja) * | 1986-04-23 | 1994-03-16 | 日本電気株式会社 | 情報処理装置 |
US4809169A (en) * | 1986-04-23 | 1989-02-28 | Advanced Micro Devices, Inc. | Parallel, multiple coprocessor computer architecture having plural execution modes |
US4926318A (en) * | 1986-11-12 | 1990-05-15 | Nec Corporation | Micro processor capable of being connected with a coprocessor |
IN171198B (de) * | 1987-02-24 | 1992-08-15 | Digital Equipment Corp | |
US5226170A (en) * | 1987-02-24 | 1993-07-06 | Digital Equipment Corporation | Interface between processor and special instruction processor in digital data processing system |
JPS63226764A (ja) * | 1987-03-17 | 1988-09-21 | Fanuc Ltd | 高速浮動小数点演算システム |
EP0295646B1 (de) * | 1987-06-19 | 1996-09-11 | Hitachi, Ltd. | Arithmetik-Parallelverarbeitungseinheit und zugehöriger Kompilator |
JPH0789320B2 (ja) * | 1987-06-19 | 1995-09-27 | 株式会社日立製作所 | 演算処理装置 |
US5247628A (en) * | 1987-11-30 | 1993-09-21 | International Business Machines Corporation | Parallel processor instruction dispatch apparatus with interrupt handler |
JP2738692B2 (ja) * | 1988-01-29 | 1998-04-08 | 株式会社日立製作所 | 並列化コンパイル方法 |
JP2754825B2 (ja) * | 1989-02-03 | 1998-05-20 | 日本電気株式会社 | マイクロプロセッサ |
US5257358A (en) * | 1989-04-18 | 1993-10-26 | Nec Electronics, Inc. | Method for counting the number of program instruction completed by a microprocessor |
US5218711A (en) * | 1989-05-15 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Microprocessor having program counter registers for its coprocessors |
-
1991
- 1991-07-03 JP JP3162631A patent/JP2884831B2/ja not_active Expired - Fee Related
-
1992
- 1992-07-01 DE DE69230118T patent/DE69230118T2/de not_active Expired - Fee Related
- 1992-07-01 EP EP92111156A patent/EP0521486B1/de not_active Expired - Lifetime
-
1995
- 1995-03-16 US US08/405,925 patent/US5530889A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE69230118D1 (de) | 1999-11-18 |
JPH06131181A (ja) | 1994-05-13 |
JP2884831B2 (ja) | 1999-04-19 |
EP0521486A2 (de) | 1993-01-07 |
US5530889A (en) | 1996-06-25 |
EP0521486B1 (de) | 1999-10-13 |
EP0521486A3 (de) | 1994-03-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |