DE69229118D1 - Generatorarchitektur für Einzeltor RAM mit Hochleistungsfähigkeit - Google Patents

Generatorarchitektur für Einzeltor RAM mit Hochleistungsfähigkeit

Info

Publication number
DE69229118D1
DE69229118D1 DE69229118T DE69229118T DE69229118D1 DE 69229118 D1 DE69229118 D1 DE 69229118D1 DE 69229118 T DE69229118 T DE 69229118T DE 69229118 T DE69229118 T DE 69229118T DE 69229118 D1 DE69229118 D1 DE 69229118D1
Authority
DE
Germany
Prior art keywords
high performance
port ram
generator architecture
architecture
generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69229118T
Other languages
English (en)
Other versions
DE69229118T2 (de
Inventor
Rajamohan Varambally
Andrea Baroni
Luigi Carro
Giovanni Mastro Mastrodomenico
Michele C O Sgs-Tho Tagliercio
Piero C O Sgs-Thomso Capocelli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69229118D1 publication Critical patent/DE69229118D1/de
Application granted granted Critical
Publication of DE69229118T2 publication Critical patent/DE69229118T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
DE69229118T 1992-11-30 1992-11-30 Generatorarchitektur für Einzeltor RAM mit Hochleistungsfähigkeit Expired - Fee Related DE69229118T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92830644A EP0600142B1 (de) 1992-11-30 1992-11-30 Generatorarchitektur für Einzeltor RAM mit Hochleistungsfähigkeit

Publications (2)

Publication Number Publication Date
DE69229118D1 true DE69229118D1 (de) 1999-06-10
DE69229118T2 DE69229118T2 (de) 1999-08-26

Family

ID=8212207

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229118T Expired - Fee Related DE69229118T2 (de) 1992-11-30 1992-11-30 Generatorarchitektur für Einzeltor RAM mit Hochleistungsfähigkeit

Country Status (4)

Country Link
US (2) US5471428A (de)
EP (1) EP0600142B1 (de)
JP (1) JP3242771B2 (de)
DE (1) DE69229118T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0600142B1 (de) * 1992-11-30 1999-05-06 STMicroelectronics S.r.l. Generatorarchitektur für Einzeltor RAM mit Hochleistungsfähigkeit
FR2713008B1 (fr) * 1993-11-23 1995-12-22 Sgs Thomson Microelectronics Mémoire non volatile modifiable électriquement avec contrôle d'écriture.
US5844994A (en) * 1995-08-28 1998-12-01 Intel Corporation Automatic microphone calibration for video teleconferencing
US5596539A (en) * 1995-12-28 1997-01-21 Lsi Logic Corporation Method and apparatus for a low power self-timed memory control system
US5870411A (en) * 1996-12-13 1999-02-09 International Business Machines Corporation Method and system for testing self-timed circuitry
US5912900A (en) * 1996-12-13 1999-06-15 International Business Machines Corporation Method and system for testing self-timed circuitry
US5883844A (en) * 1997-05-23 1999-03-16 Stmicroelectronics, Inc. Method of stress testing integrated circuit having memory and integrated circuit having stress tester for memory thereof
EP0911747B1 (de) * 1997-10-20 2004-01-02 STMicroelectronics S.r.l. CAD für redundante Speichervorrichtungen
US6044024A (en) * 1998-01-14 2000-03-28 International Business Machines Corporation Interactive method for self-adjusted access on embedded DRAM memory macros
GB2338808B (en) * 1998-06-23 2002-02-27 Mitel Semiconductor Ltd Semiconductor memories
KR100388319B1 (ko) 1998-12-30 2003-10-10 주식회사 하이닉스반도체 로우디코딩어레이의출력신호배치구조
US6002633A (en) * 1999-01-04 1999-12-14 International Business Machines Corporation Performance optimizing compiler for building a compiled SRAM
GB9902561D0 (en) * 1999-02-06 1999-03-24 Mitel Semiconductor Ltd Synchronous memory
KR100318264B1 (ko) 1999-06-28 2001-12-24 박종섭 패킷명령어 구동형 메모리소자의 로드신호 발생회로
US6141255A (en) * 1999-09-02 2000-10-31 Advanced Micro Devices, Inc. 1 transistor cell for EEPROM application
JP2001175372A (ja) * 1999-12-22 2001-06-29 Mitsubishi Electric Corp 半導体装置およびこれを用いたシステム
JP4339532B2 (ja) * 2001-07-25 2009-10-07 富士通マイクロエレクトロニクス株式会社 セルフタイミング回路を有するスタティックメモリ
KR100454259B1 (ko) * 2001-11-02 2004-10-26 주식회사 하이닉스반도체 모니터링회로를 가지는 반도체메모리장치
KR100406539B1 (ko) * 2001-12-24 2003-11-20 주식회사 하이닉스반도체 센스앰프 오버 드라이버 스킴에서의 소모전류 감소를 위한반도체 메모리 장치 및 그 방법
JP4639030B2 (ja) * 2002-11-18 2011-02-23 パナソニック株式会社 半導体記憶装置
JP4459527B2 (ja) * 2002-12-18 2010-04-28 パナソニック株式会社 半導体記憶装置
US7835598B2 (en) 2004-12-21 2010-11-16 Halliburton Energy Services, Inc. Multi-channel array processor
EP1674833A3 (de) 2004-12-21 2007-05-30 Davidson Instruments, Inc. Faseroptisches Sensorsystem
EP1869737B1 (de) 2005-03-16 2021-05-12 Davidson Instruments, Inc. Hochintensitäts-fabry-perot-sensor
WO2007033069A2 (en) 2005-09-13 2007-03-22 Davidson Instruments Inc. Tracking algorithm for linear array signal processor for fabry-perot cross-correlation pattern and method of using same
US7684051B2 (en) 2006-04-18 2010-03-23 Halliburton Energy Services, Inc. Fiber optic seismic sensor based on MEMS cantilever
US7499347B2 (en) * 2006-08-09 2009-03-03 Qualcomm Incorporated Self-timing circuit with programmable delay and programmable accelerator circuits
JP2008097787A (ja) * 2006-10-16 2008-04-24 Toshiba Corp 半導体記憶装置
US7787128B2 (en) 2007-01-24 2010-08-31 Halliburton Energy Services, Inc. Transducer for measuring environmental parameters
JP5240056B2 (ja) * 2009-05-12 2013-07-17 富士通セミコンダクター株式会社 半導体メモリおよびシステム
US9263100B2 (en) * 2013-11-29 2016-02-16 Freescale Semiconductor, Inc. Bypass system and method that mimics clock to data memory read timing

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4339766A (en) * 1979-10-11 1982-07-13 Texas Instruments Incorporated Dummy columns for reducing pattern sensitivity in MOS/LSI dynamic RAM
JPS63237296A (ja) * 1987-03-25 1988-10-03 Toshiba Corp 半導体記憶装置
JPH0642318B2 (ja) * 1988-01-18 1994-06-01 株式会社東芝 半導体メモリ
US4926387A (en) * 1988-12-27 1990-05-15 Intel Corporation Memory timing circuit employing scaled-down models of bit lines using reduced number of memory cells
JPH02201797A (ja) * 1989-01-31 1990-08-09 Toshiba Corp 半導体メモリ装置
GB8923037D0 (en) * 1989-10-12 1989-11-29 Inmos Ltd Timing control for a memory
EP0600142B1 (de) * 1992-11-30 1999-05-06 STMicroelectronics S.r.l. Generatorarchitektur für Einzeltor RAM mit Hochleistungsfähigkeit

Also Published As

Publication number Publication date
US5703821A (en) 1997-12-30
JP3242771B2 (ja) 2001-12-25
EP0600142A1 (de) 1994-06-08
JPH076182A (ja) 1995-01-10
US5471428A (en) 1995-11-28
DE69229118T2 (de) 1999-08-26
EP0600142B1 (de) 1999-05-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee