DE69228099D1 - Verfahren zur Herstellung von Sacklöchern und hergestellte Struktur - Google Patents

Verfahren zur Herstellung von Sacklöchern und hergestellte Struktur

Info

Publication number
DE69228099D1
DE69228099D1 DE69228099T DE69228099T DE69228099D1 DE 69228099 D1 DE69228099 D1 DE 69228099D1 DE 69228099 T DE69228099 T DE 69228099T DE 69228099 T DE69228099 T DE 69228099T DE 69228099 D1 DE69228099 D1 DE 69228099D1
Authority
DE
Germany
Prior art keywords
blind holes
making blind
making
holes
blind
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69228099T
Other languages
English (en)
Other versions
DE69228099T2 (de
Inventor
Fusen E Chen
Fu-Tai Liou
Girish A Dixit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69228099D1 publication Critical patent/DE69228099D1/de
Application granted granted Critical
Publication of DE69228099T2 publication Critical patent/DE69228099T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69228099T 1991-09-23 1992-09-08 Verfahren zur Herstellung von Sacklöchern und hergestellte Struktur Expired - Fee Related DE69228099T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US76394791A 1991-09-23 1991-09-23

Publications (2)

Publication Number Publication Date
DE69228099D1 true DE69228099D1 (de) 1999-02-18
DE69228099T2 DE69228099T2 (de) 1999-05-20

Family

ID=25069269

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69228099T Expired - Fee Related DE69228099T2 (de) 1991-09-23 1992-09-08 Verfahren zur Herstellung von Sacklöchern und hergestellte Struktur

Country Status (4)

Country Link
US (1) US5593921A (de)
EP (1) EP0534631B1 (de)
JP (1) JPH05211241A (de)
DE (1) DE69228099T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5395785A (en) * 1993-12-17 1995-03-07 Sgs-Thomson Microelectronics, Inc. SRAM cell fabrication with interlevel dielectric planarization
KR0138307B1 (ko) * 1994-12-14 1998-06-01 김광호 반도체 장치의 측면콘택 형성방법
US5904559A (en) * 1996-03-06 1999-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional contact or via structure with multiple sidewall contacts
US5661084A (en) * 1996-10-04 1997-08-26 Taiwan Semiconductor Manufacturing Company, Ltd Method for contact profile improvement
US5858254A (en) * 1997-01-28 1999-01-12 International Business Machines Corporation Multilayered circuitized substrate and method of fabrication
US6143655A (en) 1998-02-25 2000-11-07 Micron Technology, Inc. Methods and structures for silver interconnections in integrated circuits
US6121126A (en) * 1998-02-25 2000-09-19 Micron Technologies, Inc. Methods and structures for metal interconnections in integrated circuits
US5920121A (en) * 1998-02-25 1999-07-06 Micron Technology, Inc. Methods and structures for gold interconnections in integrated circuits
US6492694B2 (en) 1998-02-27 2002-12-10 Micron Technology, Inc. Highly conductive composite polysilicon gate for CMOS integrated circuits
US6815303B2 (en) * 1998-04-29 2004-11-09 Micron Technology, Inc. Bipolar transistors with low-resistance emitter contacts
US6025261A (en) 1998-04-29 2000-02-15 Micron Technology, Inc. Method for making high-Q inductive elements
US6696746B1 (en) 1998-04-29 2004-02-24 Micron Technology, Inc. Buried conductors
US6624515B1 (en) 2002-03-11 2003-09-23 Micron Technology, Inc. Microelectronic die including low RC under-layer interconnects
US20050149169A1 (en) * 2003-04-08 2005-07-07 Xingwu Wang Implantable medical device
US20050278020A1 (en) * 2003-04-08 2005-12-15 Xingwu Wang Medical device
US20050244337A1 (en) * 2003-04-08 2005-11-03 Xingwu Wang Medical device with a marker
US20050240100A1 (en) * 2003-04-08 2005-10-27 Xingwu Wang MRI imageable medical device
US20050261763A1 (en) * 2003-04-08 2005-11-24 Xingwu Wang Medical device
US20050149002A1 (en) * 2003-04-08 2005-07-07 Xingwu Wang Markers for visualizing interventional medical devices
US20070027532A1 (en) * 2003-12-22 2007-02-01 Xingwu Wang Medical device
KR100602131B1 (ko) * 2004-12-30 2006-07-19 동부일렉트로닉스 주식회사 반도체 소자 및 그의 제조방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900004968B1 (ko) * 1984-02-10 1990-07-12 후지쓰 가부시끼가이샤 반도체장치 제조방법
US4523372A (en) * 1984-05-07 1985-06-18 Motorola, Inc. Process for fabricating semiconductor device
US4767724A (en) * 1986-03-27 1988-08-30 General Electric Company Unframed via interconnection with dielectric etch stop
US4676867A (en) * 1986-06-06 1987-06-30 Rockwell International Corporation Planarization process for double metal MOS using spin-on glass as a sacrificial layer
US5110712A (en) * 1987-06-12 1992-05-05 Hewlett-Packard Company Incorporation of dielectric layers in a semiconductor
US4902533A (en) * 1987-06-19 1990-02-20 Motorola, Inc. Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide
JP2659714B2 (ja) * 1987-07-21 1997-09-30 株式会社日立製作所 半導体集積回路装置
US4894351A (en) * 1988-02-16 1990-01-16 Sprague Electric Company Method for making a silicon IC with planar double layer metal conductors system
US5068711A (en) * 1989-03-20 1991-11-26 Fujitsu Limited Semiconductor device having a planarized surface
US5252516A (en) * 1992-02-20 1993-10-12 International Business Machines Corporation Method for producing interlevel stud vias

Also Published As

Publication number Publication date
EP0534631B1 (de) 1999-01-07
JPH05211241A (ja) 1993-08-20
DE69228099T2 (de) 1999-05-20
US5593921A (en) 1997-01-14
EP0534631A1 (de) 1993-03-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee