DE69226309T2 - Steuerschaltung für Zwei-Tor-Speicher - Google Patents

Steuerschaltung für Zwei-Tor-Speicher

Info

Publication number
DE69226309T2
DE69226309T2 DE69226309T DE69226309T DE69226309T2 DE 69226309 T2 DE69226309 T2 DE 69226309T2 DE 69226309 T DE69226309 T DE 69226309T DE 69226309 T DE69226309 T DE 69226309T DE 69226309 T2 DE69226309 T2 DE 69226309T2
Authority
DE
Germany
Prior art keywords
control circuit
port memory
port
memory
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69226309T
Other languages
English (en)
Other versions
DE69226309D1 (de
Inventor
Bahador Rastegar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69226309D1 publication Critical patent/DE69226309D1/de
Application granted granted Critical
Publication of DE69226309T2 publication Critical patent/DE69226309T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69226309T 1991-04-30 1992-04-30 Steuerschaltung für Zwei-Tor-Speicher Expired - Fee Related DE69226309T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/693,670 US5428632A (en) 1991-04-30 1991-04-30 Control circuit for dual port memory

Publications (2)

Publication Number Publication Date
DE69226309D1 DE69226309D1 (de) 1998-08-27
DE69226309T2 true DE69226309T2 (de) 1998-12-03

Family

ID=24785623

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69226309T Expired - Fee Related DE69226309T2 (de) 1991-04-30 1992-04-30 Steuerschaltung für Zwei-Tor-Speicher

Country Status (4)

Country Link
US (1) US5428632A (de)
EP (1) EP0514049B1 (de)
JP (1) JPH05210596A (de)
DE (1) DE69226309T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6161208A (en) * 1994-05-06 2000-12-12 International Business Machines Corporation Storage subsystem including an error correcting cache and means for performing memory to memory transfers
EP3404546B1 (de) * 2017-05-16 2019-09-11 Melexis Technologies NV Vorrichtung zur überwachung und initialisierung von ports

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3566093A (en) * 1968-03-29 1971-02-23 Honeywell Inc Diagnostic method and implementation for data processors
US4483003A (en) * 1982-07-21 1984-11-13 At&T Bell Laboratories Fast parity checking in cache tag memory
US4843542A (en) * 1986-11-12 1989-06-27 Xerox Corporation Virtual memory cache for use in multi-processing systems
US4977498A (en) * 1988-04-01 1990-12-11 Digital Equipment Corporation Data processing system having a data memory interlock coherency scheme
US4918695A (en) * 1988-08-30 1990-04-17 Unisys Corporation Failure detection for partial write operations for memories
US4920536A (en) * 1988-10-14 1990-04-24 Amdahl Corporation Error recovery scheme for destaging cache data in a multi-memory system

Also Published As

Publication number Publication date
EP0514049A2 (de) 1992-11-19
JPH05210596A (ja) 1993-08-20
US5428632A (en) 1995-06-27
DE69226309D1 (de) 1998-08-27
EP0514049B1 (de) 1998-07-22
EP0514049A3 (de) 1994-08-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee