DE69221671D1 - Trockenätzverfahren mit einer (SN)x Polymer-Maske - Google Patents

Trockenätzverfahren mit einer (SN)x Polymer-Maske

Info

Publication number
DE69221671D1
DE69221671D1 DE69221671T DE69221671T DE69221671D1 DE 69221671 D1 DE69221671 D1 DE 69221671D1 DE 69221671 T DE69221671 T DE 69221671T DE 69221671 T DE69221671 T DE 69221671T DE 69221671 D1 DE69221671 D1 DE 69221671D1
Authority
DE
Germany
Prior art keywords
etching process
dry etching
polymer mask
mask
polymer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69221671T
Other languages
English (en)
Other versions
DE69221671T2 (de
Inventor
Shingo C O Sony Corpo Kadomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE69221671D1 publication Critical patent/DE69221671D1/de
Application granted granted Critical
Publication of DE69221671T2 publication Critical patent/DE69221671T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • ing And Chemical Polishing (AREA)
DE69221671T 1991-06-03 1992-06-02 Trockenätzverfahren mit einer (SN)x Polymer-Maske Expired - Fee Related DE69221671T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP15747991 1991-06-03
JP29049291 1991-10-11
JP04378392A JP3371143B2 (ja) 1991-06-03 1992-02-28 ドライエッチング方法

Publications (2)

Publication Number Publication Date
DE69221671D1 true DE69221671D1 (de) 1997-09-25
DE69221671T2 DE69221671T2 (de) 1998-03-19

Family

ID=27291666

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69221671T Expired - Fee Related DE69221671T2 (de) 1991-06-03 1992-06-02 Trockenätzverfahren mit einer (SN)x Polymer-Maske

Country Status (4)

Country Link
US (1) US5326431A (de)
EP (1) EP0517165B1 (de)
JP (1) JP3371143B2 (de)
DE (1) DE69221671T2 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3191407B2 (ja) * 1991-08-29 2001-07-23 ソニー株式会社 配線形成方法
US5176792A (en) * 1991-10-28 1993-01-05 At&T Bell Laboratories Method for forming patterned tungsten layers
JP3198586B2 (ja) * 1992-02-14 2001-08-13 ソニー株式会社 ドライエッチング方法
JPH06140396A (ja) * 1992-10-23 1994-05-20 Yamaha Corp 半導体装置とその製法
JP2804700B2 (ja) * 1993-03-31 1998-09-30 富士通株式会社 半導体装置の製造装置及び半導体装置の製造方法
DE4317623C2 (de) * 1993-05-27 2003-08-21 Bosch Gmbh Robert Verfahren und Vorrichtung zum anisotropen Plasmaätzen von Substraten und dessen Verwendung
JP3284687B2 (ja) * 1993-08-31 2002-05-20 ソニー株式会社 配線パターンの製造方法
JPH0786244A (ja) * 1993-09-13 1995-03-31 Sony Corp ドライエッチング方法
US5910021A (en) * 1994-07-04 1999-06-08 Yamaha Corporation Manufacture of semiconductor device with fine pattens
KR960005761A (ko) * 1994-07-27 1996-02-23 이데이 노부유끼 반도체장치
JPH09509017A (ja) * 1995-03-08 1997-09-09 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 酸化物／ポリサイド構造をプラズマ・エッチングするための方法
EP0740330A3 (de) * 1995-04-28 1998-05-13 Texas Instruments Incorporated Verfahren zur Verminderung der Auswirkungen von stehenden Wellen in einem Photolithographieverfahren
JP3538970B2 (ja) * 1995-05-24 2004-06-14 ヤマハ株式会社 配線形成法
US6716769B1 (en) 1995-06-02 2004-04-06 Micron Technology, Inc. Use of a plasma source to form a layer during the formation of a semiconductor device
US7294578B1 (en) 1995-06-02 2007-11-13 Micron Technology, Inc. Use of a plasma source to form a layer during the formation of a semiconductor device
US5950092A (en) * 1995-06-02 1999-09-07 Micron Technology, Inc. Use of a plasma source to form a layer during the formation of a semiconductor device
US6150250A (en) * 1995-07-05 2000-11-21 Yamaha Corporation Conductive layer forming method using etching mask with direction <200>
US5644153A (en) * 1995-10-31 1997-07-01 Micron Technology, Inc. Method for etching nitride features in integrated circuit construction
US5672243A (en) * 1995-11-28 1997-09-30 Mosel Vitelic, Inc. Antireflection coating for highly reflective photolithographic layers comprising chromium oxide or chromium suboxide
EP0948033B1 (de) * 1996-10-30 2006-10-18 Japan as represented by Director-General, Agency of Industrial Science and Technology Verfahren zum trochenätzen und gasgemisch dafür
JP3409984B2 (ja) * 1996-11-14 2003-05-26 東京エレクトロン株式会社 半導体装置及び半導体装置の製造方法
TWI246633B (en) 1997-12-12 2006-01-01 Applied Materials Inc Method of pattern etching a low k dielectric layen
US6143476A (en) * 1997-12-12 2000-11-07 Applied Materials Inc Method for high temperature etching of patterned layers using an organic mask stack
KR100439770B1 (ko) * 1997-12-26 2004-09-18 주식회사 하이닉스반도체 반도체 장치의 제조방법
US6183940B1 (en) 1998-03-17 2001-02-06 Integrated Device Technology, Inc. Method of retaining the integrity of a photoresist pattern
US6403488B1 (en) * 1998-03-19 2002-06-11 Cypress Semiconductor Corp. Selective SAC etch process
US6103623A (en) * 1998-10-05 2000-08-15 Vanguard International Semiconductor Corporation Method for fabricating a tungsten plug structure and an overlying interconnect metal structure without a tungsten etch back or CMP procedure
US6136679A (en) * 1999-03-05 2000-10-24 Taiwan Semiconductor Manufacturing Company Gate micro-patterning process
JP2001230233A (ja) 2000-02-16 2001-08-24 Mitsubishi Electric Corp 半導体装置の製造方法
US6551942B2 (en) 2001-06-15 2003-04-22 International Business Machines Corporation Methods for etching tungsten stack structures
US6703297B1 (en) 2002-03-22 2004-03-09 Advanced Micro Devices, Inc. Method of removing inorganic gate antireflective coating after spacer formation
DE10231533A1 (de) * 2002-07-11 2004-01-29 Infineon Technologies Ag Verfahren zur Metallstrukturierung
US6886573B2 (en) * 2002-09-06 2005-05-03 Air Products And Chemicals, Inc. Plasma cleaning gas with lower global warming potential than SF6
US7344991B2 (en) 2002-12-23 2008-03-18 Tokyo Electron Limited Method and apparatus for multilayer photoresist dry development
EP1609175A1 (de) * 2003-03-31 2005-12-28 Tokyo Electron Limited Verfahren und vorrichtung zur trockenentwicklung eines mehrlagenphotoresist
US8048325B2 (en) 2003-03-31 2011-11-01 Tokyo Electron Limited Method and apparatus for multilayer photoresist dry development
JP5058478B2 (ja) * 2005-11-07 2012-10-24 東京エレクトロン株式会社 半導体装置の製造方法、プラズマ処理方法、半導体装置の製造装置、制御プログラム及びコンピュータ記憶媒体
WO2014094103A1 (en) 2012-12-18 2014-06-26 Seastar Chemicals Inc. Process and method for in-situ dry cleaning of thin film deposition reactors and thin film layers
US10607850B2 (en) * 2016-12-30 2020-03-31 American Air Liquide, Inc. Iodine-containing compounds for etching semiconductor structures

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330384A (en) * 1978-10-27 1982-05-18 Hitachi, Ltd. Process for plasma etching
JPS6050923A (ja) * 1983-08-31 1985-03-22 Hitachi Ltd プラズマ表面処理方法
EP0246514A3 (de) * 1986-05-16 1989-09-20 Air Products And Chemicals, Inc. Ätzung tiefer Nuten in monokristallinen Silizium
US4713141A (en) * 1986-09-22 1987-12-15 Intel Corporation Anisotropic plasma etching of tungsten
US4975144A (en) * 1988-03-22 1990-12-04 Semiconductor Energy Laboratory Co., Ltd. Method of plasma etching amorphous carbon films

Also Published As

Publication number Publication date
EP0517165A1 (de) 1992-12-09
JPH05160081A (ja) 1993-06-25
DE69221671T2 (de) 1998-03-19
US5326431A (en) 1994-07-05
EP0517165B1 (de) 1997-08-20
JP3371143B2 (ja) 2003-01-27

Similar Documents

Publication Publication Date Title
DE69221671D1 (de) Trockenätzverfahren mit einer (SN)x Polymer-Maske
DE69114748D1 (de) An einer Oberfläche montierter Verbinder.
DE69230419D1 (de) Gerät mit einer Mensch-Maschine-Schnittstelle
FI98681B (fi) Muuntokoodauslaite
DE68923957D1 (de) Herstellungsverfahren einer gleitvorrichtung.
BR9005121A (pt) Um aparelho transferidor
DE69610459D1 (de) Vorrichtung mit einer Halbleiterwellenleiterstruktur
DE69126149D1 (de) Trockenätzverfahren
DE3771610D1 (de) Staubsauger mit einer blasstruktureinrichtung.
DE69420838D1 (de) Messerkontakt mit einer passiven verriegelungsvorrichtung
DE69208488D1 (de) Schutzschalter mit einer thermomagnetischer Unterbaugruppe
DE69011297D1 (de) Sicherungsmutter mit einer verformbaren Gewindebohrung.
DE69010034D1 (de) Halbleiteranordnung mit einer Schutzschaltung.
DE69229013D1 (de) Polymerherstellung
DE69032195D1 (de) Pegelwertregelsystem in einer Empfängerschaltung
DE69006434D1 (de) Herstellungsverfahren einer Halbleiteranordnung.
DE58907795D1 (de) Baugruppe mit einer Leiterplatte.
ATA36793A (de) Elektroakustischer wandler mit einer maske
DE69211062D1 (de) Polymerherstellung
DE68925266D1 (de) Korpuskularbestrahlungsverfahren mit einer Maske
DE69112922D1 (de) Anlage mit einer Vakuumkammer.
DE69014785D1 (de) Formgebung mit einer flächenmustergebenden Maske.
DE68918630D1 (de) Ventilation einer Vakuumbehandlungsvorrichtung.
DE69515095D1 (de) Herstellungsverfahren einer Schattenmaske
DE69028159D1 (de) Silicid-Übereinstimmendes CMOS-Verfahren mit einer differenzierten Oxid-Implantierungsmaske

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee