DE69210714D1 - Durch Doppelzweck-On-Chip-Speicher implementierter Echtzeit-Cachespeicher - Google Patents

Durch Doppelzweck-On-Chip-Speicher implementierter Echtzeit-Cachespeicher

Info

Publication number
DE69210714D1
DE69210714D1 DE69210714T DE69210714T DE69210714D1 DE 69210714 D1 DE69210714 D1 DE 69210714D1 DE 69210714 T DE69210714 T DE 69210714T DE 69210714 T DE69210714 T DE 69210714T DE 69210714 D1 DE69210714 D1 DE 69210714D1
Authority
DE
Germany
Prior art keywords
dual
real
chip memory
time cache
cache implemented
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69210714T
Other languages
English (en)
Other versions
DE69210714T2 (de
Inventor
Nathan Baron
Paul Marino
Avner Goren
Eyal Melanmed-Cohen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69210714D1 publication Critical patent/DE69210714D1/de
Application granted granted Critical
Publication of DE69210714T2 publication Critical patent/DE69210714T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • G06F2212/2515—Local memory within processor subsystem being configurable for different purposes, e.g. as cache or non-cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
DE69210714T 1991-08-24 1992-06-11 Durch Doppelzweck-On-Chip-Speicher implementierter Echtzeit-Cachespeicher Expired - Fee Related DE69210714T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB919118312A GB9118312D0 (en) 1991-08-24 1991-08-24 Real time cache implemented by dual purpose on-chip memory

Publications (2)

Publication Number Publication Date
DE69210714D1 true DE69210714D1 (de) 1996-06-20
DE69210714T2 DE69210714T2 (de) 1996-12-12

Family

ID=10700497

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69210714T Expired - Fee Related DE69210714T2 (de) 1991-08-24 1992-06-11 Durch Doppelzweck-On-Chip-Speicher implementierter Echtzeit-Cachespeicher

Country Status (6)

Country Link
US (1) US5586293A (de)
EP (1) EP0529217B1 (de)
JP (1) JP3504282B2 (de)
DE (1) DE69210714T2 (de)
GB (1) GB9118312D0 (de)
HK (1) HK1000866A1 (de)

Families Citing this family (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3713312B2 (ja) * 1994-09-09 2005-11-09 株式会社ルネサステクノロジ データ処理装置
US5715420A (en) * 1995-02-10 1998-02-03 International Business Machines Corporation Method and system for efficient memory management in a data processing system utilizing a dual mode translation lookaside buffer
US6643765B1 (en) 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US6101590A (en) 1995-10-10 2000-08-08 Micro Unity Systems Engineering, Inc. Virtual memory system with local and global virtual address translation
US5822755A (en) * 1996-01-25 1998-10-13 International Business Machines Corporation Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache
US5822764A (en) * 1996-03-04 1998-10-13 Motorola, Inc. Method and circuit for efficiently replacing invalid locked portions of a cache with valid data
US5687131A (en) * 1996-03-22 1997-11-11 Sharp Microelectronics Technology, Inc. Multi-mode cache structure
US5781926A (en) * 1996-05-20 1998-07-14 Integrated Device Technology, Inc. Method and apparatus for sub cache line access and storage allowing access to sub cache lines before completion of line fill
US5835929A (en) * 1996-05-20 1998-11-10 Integrated Device Technology, Inc. Method and apparatus for sub cache line access and storage allowing access to sub cache lines before completion of a line fill
US5974506A (en) * 1996-06-28 1999-10-26 Digital Equipment Corporation Enabling mirror, nonmirror and partial mirror cache modes in a dual cache system
US5778432A (en) * 1996-07-01 1998-07-07 Motorola, Inc. Method and apparatus for performing different cache replacement algorithms for flush and non-flush operations in response to a cache flush control bit register
US6195674B1 (en) * 1997-04-30 2001-02-27 Canon Kabushiki Kaisha Fast DCT apparatus
US6678790B1 (en) * 1997-06-09 2004-01-13 Hewlett-Packard Development Company, L.P. Microprocessor chip having a memory that is reconfigurable to function as on-chip main memory or an on-chip cache
US6321318B1 (en) * 1997-12-31 2001-11-20 Texas Instruments Incorporated User-configurable on-chip program memory system
US6055650A (en) * 1998-04-06 2000-04-25 Advanced Micro Devices, Inc. Processor configured to detect program phase changes and to adapt thereto
JPH11306084A (ja) * 1998-04-23 1999-11-05 Fujitsu Ltd 情報処理装置及び記憶媒体
US6157981A (en) * 1998-05-27 2000-12-05 International Business Machines Corporation Real time invariant behavior cache
US6560674B1 (en) * 1998-10-14 2003-05-06 Hitachi, Ltd. Data cache system
EP1111511B1 (de) * 1999-12-06 2017-09-27 Texas Instruments France Cachespeicher mit mehreren Füllungsmoden
US6397301B1 (en) * 1999-12-29 2002-05-28 Intel Corporation Preventing access to secure area of a cache
US8019943B2 (en) * 2000-01-06 2011-09-13 Super Talent Electronics, Inc. High endurance non-volatile memory devices
AU2001233131A1 (en) * 2000-02-02 2001-08-14 Sony Electronics Inc. System and method for effectively utilizing a cache memory in an electronic device
US6629187B1 (en) * 2000-02-18 2003-09-30 Texas Instruments Incorporated Cache memory controlled by system address properties
US6848024B1 (en) * 2000-08-07 2005-01-25 Broadcom Corporation Programmably disabling one or more cache entries
US6748492B1 (en) 2000-08-07 2004-06-08 Broadcom Corporation Deterministic setting of replacement policy in a cache through way selection
US6732234B1 (en) * 2000-08-07 2004-05-04 Broadcom Corporation Direct access mode for a cache
EP1182563B1 (de) * 2000-08-21 2009-09-02 Texas Instruments France Cache-Speicher mit DMA und schmutzigen Bits
EP1182562B1 (de) * 2000-08-21 2011-05-11 Texas Instruments France Intelligenter Cache-Speicher mit unterbrechbarer Blockvorausholung
EP1182564A3 (de) * 2000-08-21 2004-07-28 Texas Instruments France Lokaler Speicher mit Anzeigesbits zur Unterstützung von gleichzeitigem DMA- und CPU-Zugriff
EP1182561B1 (de) 2000-08-21 2011-10-05 Texas Instruments France Cache-Speicher mit Blockvorausholung und DMA
EP1182565B1 (de) 2000-08-21 2012-09-05 Texas Instruments France Cache-Speicher und DMA mit globalem Gültigkeitsbit
US6748495B2 (en) 2001-05-15 2004-06-08 Broadcom Corporation Random generator
US6823427B1 (en) * 2001-05-16 2004-11-23 Advanced Micro Devices, Inc. Sectored least-recently-used cache replacement
US7246220B1 (en) * 2001-07-27 2007-07-17 Magnum Semiconductor, Inc. Architecture for hardware-assisted context switching between register groups dedicated to time-critical or non-time critical tasks without saving state
WO2003042837A1 (fr) * 2001-11-16 2003-05-22 Renesas Technology Corp. Circuit integre semi-conducteur
JP3820999B2 (ja) * 2002-01-25 2006-09-13 ソニー株式会社 近接通信システム及び近接通信方法、データ管理装置及びデータ管理方法、記憶媒体、並びにコンピュータ・プログラム
US6938126B2 (en) * 2002-04-12 2005-08-30 Intel Corporation Cache-line reuse-buffer
DE10221394A1 (de) * 2002-05-14 2003-12-04 Siemens Ag Verfahren zum Betreiben eines Cache-Speichers
US20040103272A1 (en) * 2002-11-27 2004-05-27 Zimmer Vincent J. Using a processor cache as RAM during platform initialization
JP4713077B2 (ja) * 2003-03-26 2011-06-29 パナソニック株式会社 半導体装置
FR2856814B1 (fr) * 2003-06-25 2005-09-30 St Microelectronics Sa Procede de controle d'une memoire cache, et dispositif de memoire cache correspondant
US7167952B2 (en) * 2003-09-17 2007-01-23 International Business Machines Corporation Method and system for performing a memory-mode write to cache
AT500858B8 (de) * 2004-08-17 2007-02-15 Martin Schoeberl Instruction cache für echtzeitsysteme
US7613870B2 (en) * 2004-11-18 2009-11-03 International Business Machines Corporation Efficient memory usage in systems including volatile and high-density memories
US7376791B2 (en) * 2005-04-06 2008-05-20 Mediatek Inc. Memory access systems and methods for configuring ways as cache or directly addressable memory
US20080201528A1 (en) * 2005-04-06 2008-08-21 Mediatek Inc. Memory access systems for configuring ways as cache or directly addressable memory
US7653785B2 (en) * 2005-06-22 2010-01-26 Lexmark International, Inc. Reconfigurable cache controller utilizing multiple ASIC SRAMS
US8069308B2 (en) * 2008-02-13 2011-11-29 Honeywell International Inc. Cache pooling for computing systems
US8499120B2 (en) * 2008-10-17 2013-07-30 Seagate Technology Llc User selectable caching management
US20120072632A1 (en) * 2010-09-17 2012-03-22 Paul Kimelman Deterministic and non-Deterministic Execution in One Processor
US9244832B1 (en) * 2013-03-15 2016-01-26 Emc Corporation Cache learning model
KR102117511B1 (ko) * 2013-07-30 2020-06-02 삼성전자주식회사 프로세서 및 메모리 제어 방법
GB2517453B (en) * 2013-08-20 2017-12-20 Imagination Tech Ltd Improved use of memory resources
KR102219288B1 (ko) * 2013-12-09 2021-02-23 삼성전자 주식회사 캐시 모드 및 메모리 모드 동작을 지원하는 메모리 장치 및 이의 동작 방법
US9767041B2 (en) * 2015-05-26 2017-09-19 Intel Corporation Managing sectored cache
US11556477B2 (en) * 2018-06-15 2023-01-17 Arteris, Inc. System and method for configurable cache IP with flushable address range
US11409643B2 (en) 2019-11-06 2022-08-09 Honeywell International Inc Systems and methods for simulating worst-case contention to determine worst-case execution time of applications executed on a processor

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging
US4195341A (en) * 1977-12-22 1980-03-25 Honeywell Information Systems Inc. Initialization of cache store to assure valid data
US4513367A (en) * 1981-03-23 1985-04-23 International Business Machines Corporation Cache locking controls in a multiprocessor
JPS58102381A (ja) * 1981-12-15 1983-06-17 Nec Corp バツフアメモリ
US4602368A (en) * 1983-04-15 1986-07-22 Honeywell Information Systems Inc. Dual validity bit arrays
US4669043A (en) * 1984-02-17 1987-05-26 Signetics Corporation Memory access controller
US4788656A (en) * 1984-05-25 1988-11-29 The Johns Hopkins University Cache memory and pre-processor
US5155833A (en) * 1987-05-11 1992-10-13 At&T Bell Laboratories Multi-purpose cache memory selectively addressable either as a boot memory or as a cache memory
US5025366A (en) * 1988-01-20 1991-06-18 Advanced Micro Devices, Inc. Organization of an integrated cache unit for flexible usage in cache system design
US4977498A (en) * 1988-04-01 1990-12-11 Digital Equipment Corporation Data processing system having a data memory interlock coherency scheme
US5159676A (en) * 1988-12-05 1992-10-27 Micron Technology, Inc. Semi-smart DRAM controller IC to provide a pseudo-cache mode of operation using standard page mode draws
JPH0680499B2 (ja) * 1989-01-13 1994-10-12 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムのキャッシュ制御システムおよび方法
JPH0740247B2 (ja) * 1989-06-20 1995-05-01 松下電器産業株式会社 キャッシュメモリ装置
US5297270A (en) * 1989-11-13 1994-03-22 Zenith Data Systems Corporation Programmable cache memory which associates each section of main memory to be cached with a status bit which enables/disables the caching accessibility of the particular section, and with the capability of functioning with memory areas of varying size
JPH061463B2 (ja) * 1990-01-16 1994-01-05 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムおよびそのプライベート・キャッシュ制御方法
JPH0748190B2 (ja) * 1990-01-22 1995-05-24 株式会社東芝 キャッシュメモリ内蔵マイクロプロセッサ

Also Published As

Publication number Publication date
JPH05225061A (ja) 1993-09-03
HK1000866A1 (en) 1998-05-01
JP3504282B2 (ja) 2004-03-08
GB9118312D0 (en) 1991-10-09
US5586293A (en) 1996-12-17
EP0529217A1 (de) 1993-03-03
EP0529217B1 (de) 1996-05-15
DE69210714T2 (de) 1996-12-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC. (N.D.GES.D. STAATES

8339 Ceased/non-payment of the annual fee