FR2856814B1 - Procede de controle d'une memoire cache, et dispositif de memoire cache correspondant - Google Patents
Procede de controle d'une memoire cache, et dispositif de memoire cache correspondantInfo
- Publication number
- FR2856814B1 FR2856814B1 FR0307689A FR0307689A FR2856814B1 FR 2856814 B1 FR2856814 B1 FR 2856814B1 FR 0307689 A FR0307689 A FR 0307689A FR 0307689 A FR0307689 A FR 0307689A FR 2856814 B1 FR2856814 B1 FR 2856814B1
- Authority
- FR
- France
- Prior art keywords
- controlling
- memory device
- corresponding cage
- memory
- cache memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0307689A FR2856814B1 (fr) | 2003-06-25 | 2003-06-25 | Procede de controle d'une memoire cache, et dispositif de memoire cache correspondant |
US10/874,804 US20050010724A1 (en) | 2003-06-25 | 2004-06-23 | Method of controlling a cache memory, and corresponding cache memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0307689A FR2856814B1 (fr) | 2003-06-25 | 2003-06-25 | Procede de controle d'une memoire cache, et dispositif de memoire cache correspondant |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2856814A1 FR2856814A1 (fr) | 2004-12-31 |
FR2856814B1 true FR2856814B1 (fr) | 2005-09-30 |
Family
ID=33515408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0307689A Expired - Fee Related FR2856814B1 (fr) | 2003-06-25 | 2003-06-25 | Procede de controle d'une memoire cache, et dispositif de memoire cache correspondant |
Country Status (2)
Country | Link |
---|---|
US (1) | US20050010724A1 (fr) |
FR (1) | FR2856814B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9524242B2 (en) | 2014-01-28 | 2016-12-20 | Stmicroelectronics International N.V. | Cache memory system with simultaneous read-write in single cycle |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB9118312D0 (en) * | 1991-08-24 | 1991-10-09 | Motorola Inc | Real time cache implemented by dual purpose on-chip memory |
GB9701960D0 (en) * | 1997-01-30 | 1997-03-19 | Sgs Thomson Microelectronics | A cache system |
US6434671B2 (en) * | 1997-09-30 | 2002-08-13 | Intel Corporation | Software-controlled cache memory compartmentalization |
JP3495266B2 (ja) * | 1998-11-13 | 2004-02-09 | Necエレクトロニクス株式会社 | キャッシュロック装置及びキャッシュロック方法 |
US6493800B1 (en) * | 1999-03-31 | 2002-12-10 | International Business Machines Corporation | Method and system for dynamically partitioning a shared cache |
US6859862B1 (en) * | 2000-04-07 | 2005-02-22 | Nintendo Co., Ltd. | Method and apparatus for software management of on-chip cache |
US6848024B1 (en) * | 2000-08-07 | 2005-01-25 | Broadcom Corporation | Programmably disabling one or more cache entries |
GB2368150B (en) * | 2000-10-17 | 2005-03-30 | Advanced Risc Mach Ltd | Management of caches in a data processing apparatus |
-
2003
- 2003-06-25 FR FR0307689A patent/FR2856814B1/fr not_active Expired - Fee Related
-
2004
- 2004-06-23 US US10/874,804 patent/US20050010724A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20050010724A1 (en) | 2005-01-13 |
FR2856814A1 (fr) | 2004-12-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20150227 |