AU2001233131A1 - System and method for effectively utilizing a cache memory in an electronic device - Google Patents

System and method for effectively utilizing a cache memory in an electronic device

Info

Publication number
AU2001233131A1
AU2001233131A1 AU2001233131A AU3313101A AU2001233131A1 AU 2001233131 A1 AU2001233131 A1 AU 2001233131A1 AU 2001233131 A AU2001233131 A AU 2001233131A AU 3313101 A AU3313101 A AU 3313101A AU 2001233131 A1 AU2001233131 A1 AU 2001233131A1
Authority
AU
Australia
Prior art keywords
electronic device
cache memory
effectively utilizing
utilizing
effectively
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001233131A
Inventor
David V. James
Glen D Stone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Electronics Inc
Original Assignee
Sony Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Electronics Inc filed Critical Sony Electronics Inc
Publication of AU2001233131A1 publication Critical patent/AU2001233131A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Record Information Processing For Printing (AREA)
AU2001233131A 2000-02-02 2001-01-30 System and method for effectively utilizing a cache memory in an electronic device Abandoned AU2001233131A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US49687600A 2000-02-02 2000-02-02
US09496876 2000-02-02
PCT/US2001/003025 WO2001057675A1 (en) 2000-02-02 2001-01-30 System and method for effectively utilizing a cache memory in an electronic device

Publications (1)

Publication Number Publication Date
AU2001233131A1 true AU2001233131A1 (en) 2001-08-14

Family

ID=23974551

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001233131A Abandoned AU2001233131A1 (en) 2000-02-02 2001-01-30 System and method for effectively utilizing a cache memory in an electronic device

Country Status (3)

Country Link
AU (1) AU2001233131A1 (en)
TW (1) TW502165B (en)
WO (1) WO2001057675A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7644239B2 (en) 2004-05-03 2010-01-05 Microsoft Corporation Non-volatile memory cache performance improvement
US7490197B2 (en) 2004-10-21 2009-02-10 Microsoft Corporation Using external memory devices to improve system performance
US8914557B2 (en) 2005-12-16 2014-12-16 Microsoft Corporation Optimizing write and wear performance for a memory
US7543116B2 (en) * 2006-01-30 2009-06-02 International Business Machines Corporation Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains
US7966457B2 (en) 2006-12-15 2011-06-21 Microchip Technology Incorporated Configurable cache for a microprocessor
US9208095B2 (en) 2006-12-15 2015-12-08 Microchip Technology Incorporated Configurable cache for a microprocessor
US7877537B2 (en) 2006-12-15 2011-01-25 Microchip Technology Incorporated Configurable cache for a microprocessor
US8631203B2 (en) 2007-12-10 2014-01-14 Microsoft Corporation Management of external memory functioning as virtual cache
US9032151B2 (en) 2008-09-15 2015-05-12 Microsoft Technology Licensing, Llc Method and system for ensuring reliability of cache data and metadata subsequent to a reboot
US8032707B2 (en) 2008-09-15 2011-10-04 Microsoft Corporation Managing cache data and metadata
US7953774B2 (en) 2008-09-19 2011-05-31 Microsoft Corporation Aggregation of write traffic to a data store

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4928239A (en) * 1986-06-27 1990-05-22 Hewlett-Packard Company Cache memory with variable fetch and replacement schemes
GB9118312D0 (en) * 1991-08-24 1991-10-09 Motorola Inc Real time cache implemented by dual purpose on-chip memory
US5829028A (en) * 1996-05-06 1998-10-27 Advanced Micro Devices, Inc. Data cache configured to store data in a use-once manner

Also Published As

Publication number Publication date
TW502165B (en) 2002-09-11
WO2001057675A1 (en) 2001-08-09

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