AU2001291006A1 - System and method for providing reliable transmission in a buffered memory system - Google Patents

System and method for providing reliable transmission in a buffered memory system

Info

Publication number
AU2001291006A1
AU2001291006A1 AU2001291006A AU9100601A AU2001291006A1 AU 2001291006 A1 AU2001291006 A1 AU 2001291006A1 AU 2001291006 A AU2001291006 A AU 2001291006A AU 9100601 A AU9100601 A AU 9100601A AU 2001291006 A1 AU2001291006 A1 AU 2001291006A1
Authority
AU
Australia
Prior art keywords
reliable transmission
providing reliable
buffered memory
memory system
buffered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001291006A
Inventor
Randy Bonella
James Dodd
John Halbert
Michael Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001291006A1 publication Critical patent/AU2001291006A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
AU2001291006A 2000-09-18 2001-09-14 System and method for providing reliable transmission in a buffered memory system Abandoned AU2001291006A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/664,982 2000-09-18
US09/664,982 US6530006B1 (en) 2000-09-18 2000-09-18 System and method for providing reliable transmission in a buffered memory system
PCT/US2001/028930 WO2002023352A2 (en) 2000-09-18 2001-09-14 System and method for providing reliable transmission in a buffered memory system

Publications (1)

Publication Number Publication Date
AU2001291006A1 true AU2001291006A1 (en) 2002-03-26

Family

ID=24668229

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001291006A Abandoned AU2001291006A1 (en) 2000-09-18 2001-09-14 System and method for providing reliable transmission in a buffered memory system

Country Status (8)

Country Link
US (1) US6530006B1 (en)
KR (1) KR100625128B1 (en)
CN (1) CN100412982C (en)
AU (1) AU2001291006A1 (en)
DE (1) DE10196641T1 (en)
HK (1) HK1063230A1 (en)
TW (1) TW542957B (en)
WO (1) WO2002023352A2 (en)

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US6530006B1 (en) 2000-09-18 2003-03-04 Intel Corporation System and method for providing reliable transmission in a buffered memory system
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US6877079B2 (en) * 2001-03-06 2005-04-05 Samsung Electronics Co., Ltd. Memory system having point-to-point bus configuration
US7177288B2 (en) * 2001-11-28 2007-02-13 Intel Corporation Simultaneous transmission and reception of signals in different frequency bands over a bus line
US7013359B1 (en) * 2001-12-21 2006-03-14 Cypress Semiconductor Corporation High speed memory interface system and method
US7389387B2 (en) * 2001-12-31 2008-06-17 Intel Corporation Distributed memory module cache writeback
US6880044B2 (en) * 2001-12-31 2005-04-12 Intel Corporation Distributed memory module cache tag look-up
US6845424B2 (en) * 2002-01-31 2005-01-18 Intel Corporation Memory pass-band signaling
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US7120817B2 (en) * 2003-05-29 2006-10-10 Intel Corporation Method of signal distribution based on a standing wave within a closed loop path
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US20050050375A1 (en) * 2003-08-29 2005-03-03 Mark Novak Memory interface system and method
US7216247B2 (en) * 2004-08-05 2007-05-08 Texas Instruments Incorporated Methods and systems to reduce data skew in FIFOs
US20060129712A1 (en) * 2004-12-10 2006-06-15 Siva Raghuram Buffer chip for a multi-rank dual inline memory module (DIMM)
CN100405337C (en) * 2004-12-31 2008-07-23 技嘉科技股份有限公司 Data transmission device and method, and quick starting method for computer
US7187599B2 (en) * 2005-05-25 2007-03-06 Infineon Technologies North America Corp. Integrated circuit chip having a first delay circuit trimmed via a second delay circuit
US7562271B2 (en) * 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US7464225B2 (en) * 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7593279B2 (en) * 2006-10-11 2009-09-22 Qualcomm Incorporated Concurrent status register read
US8143720B2 (en) * 2007-02-06 2012-03-27 Rambus Inc. Semiconductor module with micro-buffers
US7508723B2 (en) * 2007-05-24 2009-03-24 Entorian Technologies, Lp Buffered memory device
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
US9201817B2 (en) 2011-08-03 2015-12-01 Montage Technology (Shanghai) Co., Ltd. Method for allocating addresses to data buffers in distributed buffer chipset
CN102915279B (en) * 2011-08-03 2015-05-13 澜起科技（上海）有限公司 Address assignment method for data registers of distributed cache chipset
US9299400B2 (en) 2012-09-28 2016-03-29 Intel Corporation Distributed row hammer tracking
US9542343B2 (en) 2012-11-29 2017-01-10 Samsung Electronics Co., Ltd. Memory modules with reduced rank loading and memory systems including same
KR20160038034A (en) 2013-07-27 2016-04-06 넷리스트 인코포레이티드 Memory module with local synchronization
US10613995B2 (en) 2015-03-16 2020-04-07 Rambus Inc. Training and operations with a double buffered memory topology
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Also Published As

Publication number Publication date
DE10196641T1 (en) 2003-08-28
CN100412982C (en) 2008-08-20
TW542957B (en) 2003-07-21
WO2002023352A3 (en) 2002-08-15
US6530006B1 (en) 2003-03-04
HK1063230A1 (en) 2004-12-17
CN1475012A (en) 2004-02-11
WO2002023352A2 (en) 2002-03-21
KR20030033070A (en) 2003-04-26
KR100625128B1 (en) 2006-09-20

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