CN100405337C - Data transmission device and method, and quick starting method for computer - Google Patents
Data transmission device and method, and quick starting method for computer Download PDFInfo
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- CN100405337C CN100405337C CNB2004101039630A CN200410103963A CN100405337C CN 100405337 C CN100405337 C CN 100405337C CN B2004101039630 A CNB2004101039630 A CN B2004101039630A CN 200410103963 A CN200410103963 A CN 200410103963A CN 100405337 C CN100405337 C CN 100405337C
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Abstract
The present invention discloses a data transmission device and a method thereof and a quick starting method for a computer, which can solve the problem that bandwidth can not be adjusted in a computer data transmission process. The data transmission device transmits data with a chip set of the compute and comprises a data transmission control unit, a first storage device and a second storage device, wherein the data transmission control unit is used for controlling data transmission among the chip set, the first storage device and the second storage device. Therefore, when the chip set transmits the data with the first storage device, the data transmission control unit can judge whether the destination can receive the whole transmitted data, if the destination can receive the whole transmitted data, the destination directly receives all the data, or else the destination receives partial data, and the rest data is stored in the second storage device firstly. After the destination receives the previous data, the data stored in the second storage device is transmitted to the destination to receive.
Description
Technical field
The present invention relates to a kind of data transmission device and method thereof, particularly relate to chipset and data transfer between storage devices devices and methods therefor in a kind of and the computing machine, the present invention also relates to a kind of fast method of computer booting.
Background technology
Existing computer organization synoptic diagram shown in Figure 1.Central processing unit 70 is via 71 pairs of primary memory 74 reading of data of north bridge chipset, as for South Bridge chip group 72 then is to be responsible for the access of computer peripheral device, and South Bridge chip group 72 can be passed through pci interface 721, ide interface 722 or I/O chip 73 and externally be connected with peripheral unit.Generally speaking, peripheral unit that I/O chip 73 connects is to belong to transmission at a slow speed, as floppy disk, keyboard, mouse, joystick.The peripheral unit that belongs to higher speed transmission then is by pci interface 721 or ide interface 722, the display card, the network card that are connected as pci interface 721, or the hard disk that ide interface 722 connected, CD etc.
But for computing machine, hard disk is main memory storage, has the big advantage of memory capacity, the data access speed that is provided is but far away from primary memory 74, therefore when 70 pairs of hard disks of central processing unit carry out the lot of data access, be subject to the transmitting bandwidth that ide interface 722 provides, and the inside of hard disk own belongs to the mechanical type access structure, and can't provide gratifying access speed, therefore hard disk often is subject to ide interface 722 fixing and limited frequency range is provided in data transmission procedure, so that have influence on the work efficiency of computer organization integral body.Hard disk also often is used to store the place of computer booting desired data in addition, and the data access speed that hard disk is slow excessively also can cause the computer booting overlong time.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of data transmission device and method, but elasticity is adjusted transmitting bandwidth, avoid all data volumes to concentrate on single memory storage, and can promote the frequency range of transmission interface, to improve data rate, also can accelerate starting up speed simultaneously.
In order to solve the problems of the technologies described above, the invention provides a kind of data transmission device, do data transmission with a chipset of computing machine, include: first memory storage, second memory storage and Data Transmission Controlling unit, the Data Transmission Controlling unit also is electrically connected with first memory storage and this second memory storage respectively, and by Data Transmission Controlling unit controls chipset, first memory storage and second data transfer between storage devices; Therefore when carrying out data transmission between the chipset and first memory storage, the chipset or first memory storage can be the data receiver, one of Data Transmission Controlling unit judges data receiver treatable data volume whether greater than data volume that data receiver sent, if, Data Transmission Controlling unit controls data receiver receives data immediately, if not, the a part of data that the Data Transmission Controlling unit will receive this data receiver earlier are temporary in second memory storage, another part data are then directly received by the data receiver, and receive data the data receiver and finish, the data that second memory storage is stored are passed to data receiver's reception again.
Transmission interface between aforesaid Data Transmission Controlling unit and the chipset is PCI-E (PCI-Express) interface.
In order to solve the problems of the technologies described above, according to another kind of scheme of the present invention, a kind of data transmission method is provided, does data transmission, comprising: provide the Data Transmission Controlling unit to come control chip group transmission data to receive to first memory storage with a chipset of computing machine; The transmission data of Data Transmission Controlling unit receiving chip group; Whether can handle the reception total data immediately by Data Transmission Controlling unit judges first memory storage again; If first memory storage can be handled the reception total data immediately, then the transmission data of the direct receiving chip group of Data Transmission Controlling unit controls first memory storage; And if first memory storage can't be handled the reception total data immediately, then the first a part of data that first memory storage will be received in Data Transmission Controlling unit are temporary in second memory storage, another part data are then directly received by first memory storage, and receive data in first memory storage and finish, the data that second memory storage is stored are passed to first memory storage and are received again.
According to another scheme of the present invention, a kind of computing machine fast starting method is provided, comprise: provide the Data Transmission Controlling unit to be connected between chipset and the internal memory, and the data transmission between Data Transmission Controlling unit controls chipset and the internal memory, can be in internal memory with the computer on/off information stores, when starting shooting again, chipset can read the computer booting information of internal memory by the Data Transmission Controlling unit, wherein, the computer booting information that this chipset directly receives this internal memory is controlled in this Data Transmission Controlling unit when judging that this chipset can be handled the computer booting information that receives this whole internal memories immediately.Need when having off-mode in this by standby power supply, provide the storage data required power supply, but when open state just automatically by the power supply unit power supply.
Adopt data transmission device of the present invention and method thereof, when the chipset and first data transfer between storage devices, come the inbound pacing of judgment data transmission destination with the Data Transmission Controlling unit, come the elasticity adjustment partly to transmit data and be temporary in second memory storage, and be unlikely to because of the destination that to receive data speed slower, and influence the data transmission efficiency of computing machine integral body.And by using PCI-E (PCI-Express) interface, the increase that can reach transmitting bandwidth between Data Transmission Controlling unit and the chipset.In addition, computer booting information is stored in second memory storage, promptly internal memory need not arrive hard disk and read boot-strap information during computer booting, but directly reads to the internal memory that is electrically connected with the Data Transmission Controlling unit, so can reach the speed of accelerating computer booting.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is existing computer organization synoptic diagram;
Fig. 2 is the system construction drawing of a preferred embodiment of the present invention;
Fig. 3 is the process flow diagram of data transmission of the present invention;
Fig. 4 is the process flow diagram of another data transmission of the present invention; And
Fig. 5 is the process flow diagram of computer switch machine operation of the present invention.
Wherein, Reference numeral:
10 chipsets
20 Data Transmission Controlling unit
21 first memory storages
22 second memory storages
23 standby power supplies
70 central processing units
71 north bridge chipset
72 South Bridge chip groups
721 pci interfaces
722 ide interfaces
73 I/O chips
74 primary memorys
Embodiment
Fig. 2 is the system construction drawing of a preferred embodiment of the present invention.The described chipset of present embodiment 10 is for to provide PCI-E (PCI-Express) the South Bridge chip group or the north bridge chipset of interface, and this chipset 10 is electrically connected with a Data Transmission Controlling unit 20.Transmission interface between Data Transmission Controlling unit 20 and the chipset 10 is PCI-E (PCI-Express) interface, and this Data Transmission Controlling unit 20 can integrate the passage (Lane) of a plurality of PCI-E and become one, so can increase frequency range and accelerate data processing speed, the Data Transmission Controlling unit 20 of present embodiment is realized with chip.
The Data Transmission Controlling unit 20 of present embodiment is electrically connected with one first memory storage 21 and one second memory storage 22 respectively, and be used for control chip group 10, data transmission between first memory storage 21 and second memory storage 22, receive for first memory storage 21 as chipset 10 transmission data, or first memory storage, 21 transmission data receive for chipset 10, second memory storage 22 then provides the temporarily providing room in the data transmission procedure, the temporary of data can be provided, in data transmission procedure, be used for elasticity for Data Transmission Controlling unit 20 and adjust transmitting bandwidth.
Therefore can big hard disk and the fast internal memory of data access speed of external memory capacity by Data Transmission Controlling unit 20, and hard disk and internal memory promptly are respectively described first memory storage 21 of present embodiment and second memory storage 22.Because of present embodiment second memory storage 22 is an internal memory, internal memory is plugged on the memory bank that the computer main frame panel expansion is electrically connected with Data Transmission Controlling unit 20.Look the size of transmitted data amount in addition, first memory storage 21 of present embodiment and second memory storage 22 can be a plurality of designs, with speeding up data transmission speed.
Use the PCI-E interface between the chipset 10 of present embodiment and the Data Transmission Controlling unit 20, the transmitting bandwidth of PCI-E * 1 (representing one group of passage) is 250MB/S, because PCI-E plans to be had * 1, * 2, * 4, * 8, * 16, * plurality of specifications such as 32..., so when the transmitting bandwidth of PCI-E * 16 during in the full duplex operating mode up to 8GB/S, the general computer primary memory or the data access speed of hard disk of surpassing far away already.Based on this factor, second memory storage 22 of present embodiment also can be appointed as a computer booting position by Basic Input or Output System (BIOS) (BIOS), and stores computer booting information at second memory storage 22 in advance, can supply the computing machine quick turn-on.And not influenced by computer shutdown in order to ensure the data of second memory storage, 22 storages, present embodiment provides a standby power supply 23 supplies second memory storage 22 and uses when computer shutdown.Wherein the computer booting information of memory can be-a plurality of start shelves of operating system (as Windows system, OS2 system or linux system), a plurality of logfile, a plurality of execution shelves or a plurality of related shelves; Perhaps computer booting information also can be a start image file.
Fig. 3 is the process flow diagram of data transmission of the present invention.This process flow diagram provides the data transmission of 10 pairs first memory storages 21 of Data Transmission Controlling unit 20 control chip group, comprises the following steps: step S301, and chipset 10 begins to transmit data and gives first memory storage 21; Step S303, the transmission data of Data Transmission Controlling unit 20 receiving chip groups 10; Step S305, judge whether first memory storage 21 can handle the reception total data immediately, judge that by Data Transmission Controlling unit 20 21 of first memory storages can handle the data volume that receives and whether surpass chipset 10 and be transferred to the total data amount that first memory storage 21 receives.If judged result is for being, execution in step S307 then, and if be judged as and deny, then execution in step S309; Step S307, first memory storage, the 21 direct transmission data of receiving chip group 10 immediately; Step S309, a part of data that Data Transmission Controlling unit 20 is transmitted chipset 10 are temporary in second memory storage 22 earlier; Step S311, and chipset 10 transmits remaining another part data directly by 21 receptions of first memory storage; Step S313 finishes when first memory storage 21 receives data; Step S315 passes to first memory storage 21 with the data of second memory storage, 22 storages again and receives.
Fig. 4 is the process flow diagram of another data transmission of the present invention.This process flow diagram provides the data transmission of 21 pairs of chipsets 10 of Data Transmission Controlling unit 20 control first memory storages, comprises the following steps: step S401, and first memory storage 21 begins to transmit data and gives chipset 10; Step S403, Data Transmission Controlling unit 20 receives the transmission data of first memory storage 21; Step S405, judge whether chipset 10 can handle the reception total data immediately, judge that by Data Transmission Controlling unit 20 10 of chipsets can handle the data volume that receives and whether surpass first memory storage 21 and be transferred to the total data amount that chipset 10 receives, and chipset 10 is not in busy condition yet.If judged result is for being, execution in step S407 then, and if be judged as and deny, then execution in step S409; Step S407, chipset 10 directly receives the transmission data of first memory storage 21 immediately; Step S409, Data Transmission Controlling unit 20 is temporary in second memory storage 22 earlier with a part of data that first memory storage 21 is transmitted; Step S411, and first memory storage 21 transmits remaining another part data directly by chipset 10 receptions; Step S413 finishes when chipset 10 receives data, and step S415 passes to chipset 10 with the data of second memory storage, 22 storages again and receives.
So Data Transmission Controlling unit 20 that present embodiment provides, when carrying out data transmission between the may command chipset 10 and first memory storage 21, and the size of visual transmitted data amount, in the time of handling the data volume of one of reception as transmitted data amount less than the destination, then the destination directly receives the transmission of data.Otherwise, when transmitted data amount can be handled the data volume of one of reception greater than the destination, destination receiving unit data in advance in the process range that can receive data volume then, remaining data then is stored in second memory storage 22 earlier, and etc. after the destination receives the data volume of handling last pen, again the data of these second memory storage, 22 storages are passed to the destination device and receive.And the data that provided via second memory storage 22 are temporary, as the setting of high-speed cache, can allow the speed of carrying out data transmission between the chipset 10 and first memory storage 21 faster.
Fig. 5 is the process flow diagram of computer switch machine operation of the present invention.Second memory storage 22 can store computer booting information in advance, therefore when computer booting, step S501, chipset 10 reads data in second memory storage 22 by Data Transmission Controlling unit 20, can obtain the required data of computer booting fast; Step S503, computing machine enters into open state according to the computer booting information that reads; And the mode of computer booting that present embodiment provides is more quick more than the speed that tradition start obtains the start data from hard disk; Step S505, and computing machine will shut down or will enter into sleep pattern the time, earlier with the opening computer information stores in second memory storage, directly read computer booting information during for next computer booting from second memory storage 22.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (21)
1. a data transmission device is done data transmission with the chipset of computing machine, it is characterized in that, comprising:
First memory storage;
Second memory storage; And
The Data Transmission Controlling unit is electrically connected on this first memory storage and this second memory storage respectively, and this Data Transmission Controlling unit is in order to control this chipset, this first memory storage and this second data transfer between storage devices;
Wherein, when carrying out data transmission between this chipset and this first memory storage, the data receiver is one of them of this chipset and this first memory storage,
One of this data receiver of this Data Transmission Controlling unit judges treatable data volume whether greater than data volume that data receiver sent, if, then this data receiver of this Data Transmission Controlling unit controls receives data immediately, if not, then this Data Transmission Controlling unit a part of data that earlier this data receiver will be received are temporary in this second memory storage, another part data are then directly received by this data receiver, and receive data in this data receiver and finish, the data that this second memory storage is stored are passed to this data receiver and are received again.
2. data transmission device according to claim 1 is characterized in that, this first memory storage is a hard disk.
3. data transmission device according to claim 1 is characterized in that, this second memory storage is an internal memory.
4. data transmission device according to claim 1 is characterized in that, this Data Transmission Controlling unit is a chip, and this chip is used for the channel integration of a plurality of PCI-Express interfaces is become one.
5. data transmission device according to claim 1 is characterized in that, the transmission interface between this Data Transmission Controlling unit and this chipset is the PCI-Express interface.
6. data transmission device according to claim 1 is characterized in that, also comprises: a standby power supply, and in order to the electric power of this second memory storage to be provided.
7. a data transmission method is done data transmission with the chipset of computing machine, it is characterized in that, comprising:
The Data Transmission Controlling unit is provided, controls these chipset transmission data and receive for first memory storage;
This Data Transmission Controlling unit receives the transmission data of this chipset;
Whether this first memory storage of this Data Transmission Controlling unit judges can promptly handle the reception total data;
If this first memory storage can be handled the reception total data immediately, then this first memory storage of this Data Transmission Controlling unit controls directly receives the transmission data of this chipset; And
If this first memory storage can't be handled the reception total data immediately, then this Data Transmission Controlling unit is temporary in second memory storage with a part of data that this first memory storage will receive earlier, another part data are then directly received by this first memory storage, and receive data in this first memory storage and finish, the data that this second memory storage is stored are passed to this first memory storage and are received again.
8. data transmission method according to claim 7 is characterized in that, this first memory storage is a hard disk.
9. data transmission method according to claim 7 is characterized in that, this second memory storage is an internal memory.
10. data transmission method according to claim 7 is characterized in that, this Data Transmission Controlling unit is a chip, and this chip is used for the channel integration of a plurality of PCI-Express interfaces is become one.
11. data transmission method according to claim 7 is characterized in that, the transmission interface between this Data Transmission Controlling unit and this chipset is the PCI-Express interface.
12. a data transmission method is done data transmission with the chipset of computing machine, it is characterized in that, comprising:
The Data Transmission Controlling unit is provided, controls first memory storage transmission data and receive for this chipset;
This Data Transmission Controlling unit receives the transmission data of this first memory storage;
Whether this this chipset of Data Transmission Controlling unit judges can handle the reception total data immediately;
If this chipset can be handled the reception total data immediately, then this this chipset of Data Transmission Controlling unit controls directly receives the transmission data of this first memory storage; And
If this chipset can't be handled the reception total data immediately, then this Data Transmission Controlling unit a part of data that earlier this chipset will be received are temporary in second memory storage, another part data are then directly received by this chipset, and receive data in this chipset and finish, the data that this second memory storage is stored are passed to this chipset and are received again.
13. data transmission method according to claim 12 is characterized in that, this first memory storage is a hard disk.
14. data transmission method according to claim 12 is characterized in that, this second memory storage is an internal memory.
15. data transmission method according to claim 12 is characterized in that, this Data Transmission Controlling unit is a chip, and this chip is used for the channel integration of a plurality of PCI-Express interfaces is become one.
16. data transmission method according to claim 12 is characterized in that, the transmission interface between this Data Transmission Controlling unit and this chipset is the PCI-Express interface.
17. a computing machine fast starting method is characterized in that, comprising:
Provide the Data Transmission Controlling unit to be electrically connected between chipset and the internal memory, the data transmission between this this chipset of Data Transmission Controlling unit controls and the internal memory, wherein this memory has computer booting information and has obtained the power supply supply; And
When computer booting, this chipset reads the computer booting information of this internal memory by this Data Transmission Controlling unit, wherein, the computer booting information that this chipset directly receives this internal memory is controlled in this Data Transmission Controlling unit when judging that this chipset can be handled the computer booting information that receives this whole internal memories immediately.
18. computing machine fast starting method according to claim 17 is characterized in that, the transmission interface between this Data Transmission Controlling unit and this chipset is the PCI-Express interface.
19. computing machine fast starting method according to claim 17 is characterized in that, this computer booting information is a plurality of start files of operating system, a plurality of logfile, a plurality of execution shelves, a plurality of associated with or is the start image file.
20. computing machine fast starting method according to claim 17 is characterized in that, also comprises: set the specified opening device of Basic Input or Output System (BIOS) that saves as computing machine in this.
21. computing machine fast starting method according to claim 17 is characterized in that, also comprises: when computer shutdown or sleep, storage computation machine boot-strap information is to this internal memory.
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| CNB2004101039630A CN100405337C (en) | 2004-12-31 | 2004-12-31 | Data transmission device and method, and quick starting method for computer |
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| CNB2004101039630A CN100405337C (en) | 2004-12-31 | 2004-12-31 | Data transmission device and method, and quick starting method for computer |
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| CN1801123A CN1801123A (en) | 2006-07-12 |
| CN100405337C true CN100405337C (en) | 2008-07-23 |
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| CN102722389B (en) * | 2012-05-31 | 2017-08-25 | Tcl集团股份有限公司 | A kind of electronic equipment and its boot system |
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| JPH08263378A (en) * | 1995-03-22 | 1996-10-11 | Nec Ibaraki Ltd | Disk cache controller |
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2004
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| US5371855A (en) * | 1979-06-04 | 1994-12-06 | Unisys Corporation | Disc cache subsystem having plural-level cache memories |
| JPH08263378A (en) * | 1995-03-22 | 1996-10-11 | Nec Ibaraki Ltd | Disk cache controller |
| CN1282911A (en) * | 1999-07-30 | 2001-02-07 | 神基科技股份有限公司 | Method for suspending state of computer system |
| CN1475012A (en) * | 2000-09-18 | 2004-02-11 | 英特尔公司 | System and method for providing reliable transmission in buffered memory system |
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| Title |
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| 《带缓存磁盘技术PCI卡在Windows NT下的应用》. 姜戬，谢长生.计算机系统应用，第4期. 2001 |
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